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| author | Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> | 2025-06-26 11:02:39 +0200 |
|---|---|---|
| committer | Rob Clark <robin.clark@oss.qualcomm.com> | 2025-07-04 17:48:40 -0700 |
| commit | 709dd2ff2357734f5a0b2ef68e1f7c4256543a70 (patch) | |
| tree | 603f26783fabe8ee1784019562eb0427426f841b /drivers/soc | |
| parent | caf5ad18a2b49e3b20b1dc65e928851d409bcd1c (diff) | |
| download | linux-next-709dd2ff2357734f5a0b2ef68e1f7c4256543a70.tar.gz linux-next-709dd2ff2357734f5a0b2ef68e1f7c4256543a70.zip | |
soc: qcom: ubwc: Add #defines for UBWC swizzle bits
Make the values a bit more meaningful.
This commit is intentionally cross-subsystem to ease review, as the
patchset is intended to be merged together, with a maintainer
consensus.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660981/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Diffstat (limited to 'drivers/soc')
| -rw-r--r-- | drivers/soc/qcom/ubwc_config.c | 37 |
1 files changed, 25 insertions, 12 deletions
diff --git a/drivers/soc/qcom/ubwc_config.c b/drivers/soc/qcom/ubwc_config.c index 3eb2f2118e5d..816bad6674ab 100644 --- a/drivers/soc/qcom/ubwc_config.c +++ b/drivers/soc/qcom/ubwc_config.c @@ -32,7 +32,7 @@ static const struct qcom_ubwc_cfg_data qcm2290_data = { static const struct qcom_ubwc_cfg_data sa8775p_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_0, - .ubwc_swizzle = 4, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, .highest_bank_bit = 13, .macrotile_mode = true, @@ -41,7 +41,8 @@ static const struct qcom_ubwc_cfg_data sa8775p_data = { static const struct qcom_ubwc_cfg_data sar2130p_data = { .ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */ .ubwc_dec_version = UBWC_4_3, - .ubwc_swizzle = 6, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, .highest_bank_bit = 13, .macrotile_mode = true, @@ -50,7 +51,8 @@ static const struct qcom_ubwc_cfg_data sar2130p_data = { static const struct qcom_ubwc_cfg_data sc7180_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, - .ubwc_swizzle = 6, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, .highest_bank_bit = 14, }; @@ -58,7 +60,8 @@ static const struct qcom_ubwc_cfg_data sc7180_data = { static const struct qcom_ubwc_cfg_data sc7280_data = { .ubwc_enc_version = UBWC_3_0, .ubwc_dec_version = UBWC_4_0, - .ubwc_swizzle = 6, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, .highest_bank_bit = 14, .macrotile_mode = true, @@ -74,7 +77,8 @@ static const struct qcom_ubwc_cfg_data sc8180x_data = { static const struct qcom_ubwc_cfg_data sc8280xp_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_0, - .ubwc_swizzle = 6, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, .highest_bank_bit = 16, .macrotile_mode = true, @@ -95,7 +99,9 @@ static const struct qcom_ubwc_cfg_data sdm845_data = { static const struct qcom_ubwc_cfg_data sm6115_data = { .ubwc_enc_version = UBWC_1_0, .ubwc_dec_version = UBWC_2_0, - .ubwc_swizzle = 7, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, .highest_bank_bit = 14, }; @@ -103,7 +109,9 @@ static const struct qcom_ubwc_cfg_data sm6115_data = { static const struct qcom_ubwc_cfg_data sm6125_data = { .ubwc_enc_version = UBWC_1_0, .ubwc_dec_version = UBWC_3_0, - .ubwc_swizzle = 7, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 | + UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .highest_bank_bit = 14, }; @@ -116,7 +124,8 @@ static const struct qcom_ubwc_cfg_data sm6150_data = { static const struct qcom_ubwc_cfg_data sm6350_data = { .ubwc_enc_version = UBWC_2_0, .ubwc_dec_version = UBWC_2_0, - .ubwc_swizzle = 6, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, .highest_bank_bit = 14, }; @@ -136,7 +145,8 @@ static const struct qcom_ubwc_cfg_data sm8150_data = { static const struct qcom_ubwc_cfg_data sm8250_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_0, - .ubwc_swizzle = 6, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, @@ -146,7 +156,8 @@ static const struct qcom_ubwc_cfg_data sm8250_data = { static const struct qcom_ubwc_cfg_data sm8350_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_0, - .ubwc_swizzle = 6, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, @@ -156,7 +167,8 @@ static const struct qcom_ubwc_cfg_data sm8350_data = { static const struct qcom_ubwc_cfg_data sm8550_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_3, - .ubwc_swizzle = 6, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, @@ -176,7 +188,8 @@ static const struct qcom_ubwc_cfg_data sm8750_data = { static const struct qcom_ubwc_cfg_data x1e80100_data = { .ubwc_enc_version = UBWC_4_0, .ubwc_dec_version = UBWC_4_3, - .ubwc_swizzle = 6, + .ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 | + UBWC_SWIZZLE_ENABLE_LVL3, .ubwc_bank_spread = true, /* TODO: highest_bank_bit = 15 for LP_DDR4 */ .highest_bank_bit = 16, |