Merge tag 'v6.15-rc6' into next

Sync up with mainline to bring in xpad controller changes.

7 files changed, 726 insertions, 34 deletions

diff --git a/drivers/pinctrl/qcom/Kconfig.msm b/drivers/pinctrl/qcom/Kconfig.msm
index 35f47660a56b..0bb44c9a4c06 100644
--- a/drivers/pinctrl/qcom/Kconfig.msm
+++ b/drivers/pinctrl/qcom/Kconfig.msm
@@ -138,10 +138,10 @@ config PINCTRL_MSM8916
 	  Qualcomm TLMM block found on the Qualcomm 8916 platform.
 
 config PINCTRL_MSM8917
-	tristate "Qualcomm 8917 pin controller driver"
+	tristate "Qualcomm 8917/8937 pin controller driver"
 	help
 	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
-	  Qualcomm TLMM block found on the Qualcomm MSM8917 platform.
+	  Qualcomm TLMM block found on the Qualcomm MSM8917, MSM8937 platform.
 
 config PINCTRL_MSM8953
 	tristate "Qualcomm 8953 pin controller driver"
@@ -437,4 +437,14 @@ config PINCTRL_X1E80100
 	  Say Y here to compile statically, or M here to compile it as a module.
 	  If unsure, say N.
 
+config PINCTRL_TLMM_TEST
+	tristate "Qualcomm TLMM test driver"
+	depends on ARM64 || COMPILE_TEST
+	depends on KUNIT
+	help
+	  This driver provides test cases for the interrupt capabilities of
+	  TLMM driver (pinctrl-msm). Specify a floating gpio to use for testing
+	  using the module parameter "gpio" and execute the kunit suite.
+	  If unsure, say N.
+
 endif
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index 5c4100925cf9..954f5291cc37 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -71,3 +71,4 @@ obj-$(CONFIG_PINCTRL_SM8750) += pinctrl-sm8750.o
 obj-$(CONFIG_PINCTRL_SC8280XP_LPASS_LPI) += pinctrl-sc8280xp-lpass-lpi.o
 obj-$(CONFIG_PINCTRL_LPASS_LPI) += pinctrl-lpass-lpi.o
 obj-$(CONFIG_PINCTRL_X1E80100)	+= pinctrl-x1e80100.o
+obj-$(CONFIG_PINCTRL_TLMM_TEST) += tlmm-test.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 47daa47153c9..82f0cc43bbf4 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -1045,8 +1045,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	const struct msm_pingroup *g;
 	u32 intr_target_mask = GENMASK(2, 0);
 	unsigned long flags;
-	bool was_enabled;
-	u32 val;
+	u32 val, oldval;
 
 	if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) {
 		set_bit(d->hwirq, pctrl->dual_edge_irqs);
@@ -1108,8 +1107,7 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	 * internal circuitry of TLMM, toggling the RAW_STATUS
 	 * could cause the INTR_STATUS to be set for EDGE interrupts.
 	 */
-	val = msm_readl_intr_cfg(pctrl, g);
-	was_enabled = val & BIT(g->intr_raw_status_bit);
+	val = oldval = msm_readl_intr_cfg(pctrl, g);
 	val |= BIT(g->intr_raw_status_bit);
 	if (g->intr_detection_width == 2) {
 		val &= ~(3 << g->intr_detection_bit);
@@ -1162,9 +1160,11 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 	/*
 	 * The first time we set RAW_STATUS_EN it could trigger an interrupt.
 	 * Clear the interrupt.  This is safe because we have
-	 * IRQCHIP_SET_TYPE_MASKED.
+	 * IRQCHIP_SET_TYPE_MASKED. When changing the interrupt type, we could
+	 * also still have a non-matching interrupt latched, so clear whenever
+	 * making changes to the interrupt configuration.
 	 */
-	if (!was_enabled)
+	if (val != oldval)
 		msm_ack_intr_status(pctrl, g);
 
 	if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8917.c b/drivers/pinctrl/qcom/pinctrl-msm8917.c
index cff137bb3b23..350636807b07 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm8917.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm8917.c
@@ -539,6 +539,7 @@ enum msm8917_functions {
 	msm_mux_webcam_standby,
 	msm_mux_wsa_io,
 	msm_mux_wsa_irq,
+	msm_mux_wsa_reset,
 	msm_mux__,
 };
 
@@ -1123,6 +1124,10 @@ static const char * const wsa_io_groups[] = {
 	"gpio94", "gpio95",
 };
 
+static const char * const wsa_reset_groups[] = {
+	"gpio96",
+};
+
 static const char * const blsp_spi8_groups[] = {
 	"gpio96", "gpio97", "gpio98", "gpio99",
 };
@@ -1378,6 +1383,7 @@ static const struct pinfunction msm8917_functions[] = {
 	MSM_PIN_FUNCTION(webcam_standby),
 	MSM_PIN_FUNCTION(wsa_io),
 	MSM_PIN_FUNCTION(wsa_irq),
+	MSM_PIN_FUNCTION(wsa_reset),
 };
 
 static const struct msm_pingroup msm8917_groups[] = {
@@ -1616,5 +1622,5 @@ static void __exit msm8917_pinctrl_exit(void)
 }
 module_exit(msm8917_pinctrl_exit);
 
-MODULE_DESCRIPTION("Qualcomm msm8917 pinctrl driver");
+MODULE_DESCRIPTION("Qualcomm msm8917/msm8937 pinctrl driver");
 MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c
index 8fdea25d8d67..a5b38221aea8 100644
--- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c
+++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022,2025, Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2023, Linaro Limited
  */
 
@@ -467,6 +467,7 @@ enum sa8775p_functions {
 	msm_mux_edp2_lcd,
 	msm_mux_edp3_hot,
 	msm_mux_edp3_lcd,
+	msm_mux_egpio,
 	msm_mux_emac0_mcg0,
 	msm_mux_emac0_mcg1,
 	msm_mux_emac0_mcg2,
@@ -744,6 +745,13 @@ static const char * const edp3_lcd_groups[] = {
 	"gpio49",
 };
 
+static const char *const egpio_groups[] = {
+	"gpio126", "gpio127", "gpio128", "gpio129", "gpio130", "gpio131",
+	"gpio132", "gpio133", "gpio134", "gpio135", "gpio136", "gpio137",
+	"gpio138", "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
+	"gpio144", "gpio145", "gpio146", "gpio147", "gpio148",
+};
+
 static const char * const emac0_mcg0_groups[] = {
 	"gpio12",
 };
@@ -1209,6 +1217,7 @@ static const struct pinfunction sa8775p_functions[] = {
 	MSM_PIN_FUNCTION(edp2_lcd),
 	MSM_PIN_FUNCTION(edp3_hot),
 	MSM_PIN_FUNCTION(edp3_lcd),
+	MSM_PIN_FUNCTION(egpio),
 	MSM_PIN_FUNCTION(emac0_mcg0),
 	MSM_PIN_FUNCTION(emac0_mcg1),
 	MSM_PIN_FUNCTION(emac0_mcg2),
@@ -1454,29 +1463,29 @@ static const struct msm_pingroup sa8775p_groups[] = {
 	[123] = PINGROUP(123, hs2_mi2s, phase_flag, _, _, _, _, _, _, _),
 	[124] = PINGROUP(124, hs2_mi2s, phase_flag, _, _, _, _, _, _, _),
 	[125] = PINGROUP(125, hs2_mi2s, phase_flag, _, _, _, _, _, _, _),
-	[126] = PINGROUP(126, _, _, _, _, _, _, _, _, _),
-	[127] = PINGROUP(127, _, _, _, _, _, _, _, _, _),
-	[128] = PINGROUP(128, _, _, _, _, _, _, _, _, _),
-	[129] = PINGROUP(129, _, _, _, _, _, _, _, _, _),
-	[130] = PINGROUP(130, _, _, _, _, _, _, _, _, _),
-	[131] = PINGROUP(131, _, _, _, _, _, _, _, _, _),
-	[132] = PINGROUP(132, _, _, _, _, _, _, _, _, _),
-	[133] = PINGROUP(133, _, _, _, _, _, _, _, _, _),
-	[134] = PINGROUP(134, _, _, _, _, _, _, _, _, _),
-	[135] = PINGROUP(135, _, _, _, _, _, _, _, _, _),
-	[136] = PINGROUP(136, _, _, _, _, _, _, _, _, _),
-	[137] = PINGROUP(137, _, _, _, _, _, _, _, _, _),
-	[138] = PINGROUP(138, _, _, _, _, _, _, _, _, _),
-	[139] = PINGROUP(139, _, _, _, _, _, _, _, _, _),
-	[140] = PINGROUP(140, _, _, _, _, _, _, _, _, _),
-	[141] = PINGROUP(141, _, _, _, _, _, _, _, _, _),
-	[142] = PINGROUP(142, _, _, _, _, _, _, _, _, _),
-	[143] = PINGROUP(143, _, _, _, _, _, _, _, _, _),
-	[144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, _),
-	[145] = PINGROUP(145, _, _, _, _, _, _, _, _, _),
-	[146] = PINGROUP(146, _, _, _, _, _, _, _, _, _),
-	[147] = PINGROUP(147, _, _, _, _, _, _, _, _, _),
-	[148] = PINGROUP(148, _, _, _, _, _, _, _, _, _),
+	[126] = PINGROUP(126, _, _, _, _, _, _, _, _, egpio),
+	[127] = PINGROUP(127, _, _, _, _, _, _, _, _, egpio),
+	[128] = PINGROUP(128, _, _, _, _, _, _, _, _, egpio),
+	[129] = PINGROUP(129, _, _, _, _, _, _, _, _, egpio),
+	[130] = PINGROUP(130, _, _, _, _, _, _, _, _, egpio),
+	[131] = PINGROUP(131, _, _, _, _, _, _, _, _, egpio),
+	[132] = PINGROUP(132, _, _, _, _, _, _, _, _, egpio),
+	[133] = PINGROUP(133, _, _, _, _, _, _, _, _, egpio),
+	[134] = PINGROUP(134, _, _, _, _, _, _, _, _, egpio),
+	[135] = PINGROUP(135, _, _, _, _, _, _, _, _, egpio),
+	[136] = PINGROUP(136, _, _, _, _, _, _, _, _, egpio),
+	[137] = PINGROUP(137, _, _, _, _, _, _, _, _, egpio),
+	[138] = PINGROUP(138, _, _, _, _, _, _, _, _, egpio),
+	[139] = PINGROUP(139, _, _, _, _, _, _, _, _, egpio),
+	[140] = PINGROUP(140, _, _, _, _, _, _, _, _, egpio),
+	[141] = PINGROUP(141, _, _, _, _, _, _, _, _, egpio),
+	[142] = PINGROUP(142, _, _, _, _, _, _, _, _, egpio),
+	[143] = PINGROUP(143, _, _, _, _, _, _, _, _, egpio),
+	[144] = PINGROUP(144, dbg_out, _, _, _, _, _, _, _, egpio),
+	[145] = PINGROUP(145, _, _, _, _, _, _, _, _, egpio),
+	[146] = PINGROUP(146, _, _, _, _, _, _, _, _, egpio),
+	[147] = PINGROUP(147, _, _, _, _, _, _, _, _, egpio),
+	[148] = PINGROUP(148, _, _, _, _, _, _, _, _, egpio),
 	[149] = UFS_RESET(ufs_reset, 0x1a2000),
 	[150] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x199000, 15, 0),
 	[151] = SDC_QDSD_PINGROUP(sdc1_clk, 0x199000, 13, 6),
@@ -1511,6 +1520,7 @@ static const struct msm_pinctrl_soc_data sa8775p_pinctrl = {
 	.ngpios = 150,
 	.wakeirq_map = sa8775p_pdc_map,
 	.nwakeirq_map = ARRAY_SIZE(sa8775p_pdc_map),
+	.egpio_func = 9,
 };
 
 static int sa8775p_pinctrl_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/qcom/pinctrl-sm8750.c b/drivers/pinctrl/qcom/pinctrl-sm8750.c
index 1af11cd95fb0..b94fb4ee0ec3 100644
--- a/drivers/pinctrl/qcom/pinctrl-sm8750.c
+++ b/drivers/pinctrl/qcom/pinctrl-sm8750.c
@@ -46,7 +46,9 @@
 		.out_bit = 1,                                         \
 		.intr_enable_bit = 0,                                 \
 		.intr_status_bit = 0,                                 \
-		.intr_target_bit = 5,                                 \
+		.intr_wakeup_present_bit = 6,                         \
+		.intr_wakeup_enable_bit = 7,                          \
+		.intr_target_bit = 8,                                 \
 		.intr_target_kpss_val = 3,                            \
 		.intr_raw_status_bit = 4,                             \
 		.intr_polarity_bit = 1,                               \
diff --git a/drivers/pinctrl/qcom/tlmm-test.c b/drivers/pinctrl/qcom/tlmm-test.c
new file mode 100644
index 000000000000..fd02bf3a76cb
--- /dev/null
+++ b/drivers/pinctrl/qcom/tlmm-test.c
@@ -0,0 +1,663 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#define pr_fmt(fmt) "tlmm-test: " fmt
+
+#include <kunit/test.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+
+/*
+ * This TLMM test module serves the purpose of validating that the TLMM driver
+ * (pinctrl-msm) delivers expected number of interrupts in response to changing
+ * GPIO state.
+ *
+ * To achieve this without external equipment the test takes a module parameter
+ * "gpio", which the tester is expected to specify an unused and non-connected
+ * pin. The GPIO state is then driven by adjusting the bias of the pin, at
+ * suitable times through the different test cases.
+ *
+ * Upon execution, the test initialization will find the TLMM node (subject to
+ * tlmm_of_match[] allow listing) and create the necessary references
+ * dynamically, rather then relying on e.g. Devicetree and phandles.
+ */
+
+#define MSM_PULL_MASK		GENMASK(2, 0)
+#define MSM_PULL_DOWN		1
+#define MSM_PULL_UP		3
+#define TLMM_REG_SIZE		0x1000
+
+static int tlmm_test_gpio = -1;
+module_param_named(gpio, tlmm_test_gpio, int, 0600);
+
+static struct {
+	void __iomem *base;
+	void __iomem *reg;
+	int irq;
+
+	u32 low_val;
+	u32 high_val;
+} tlmm_suite;
+
+/**
+ * struct tlmm_test_priv - Per-test context
+ * @intr_count:		number of times hard handler was hit with TLMM_TEST_COUNT op set
+ * @thread_count:	number of times thread handler was hit with TLMM_TEST_COUNT op set
+ * @intr_op:		operations to be performed by the hard IRQ handler
+ * @intr_op_remain:	number of times the TLMM_TEST_THEN_* operations should be
+ *			performed by the hard IRQ handler
+ * @thread_op:		operations to be performed by the threaded IRQ handler
+ * @thread_op_remain:	number of times the TLMM_TEST_THEN_* operations should
+ *			be performed by the threaded IRQ handler
+ */
+struct tlmm_test_priv {
+	atomic_t intr_count;
+	atomic_t thread_count;
+
+	unsigned int intr_op;
+	atomic_t intr_op_remain;
+
+	unsigned int thread_op;
+	atomic_t thread_op_remain;
+};
+
+/* Operation masks for @intr_op and @thread_op */
+#define TLMM_TEST_COUNT		BIT(0)
+#define TLMM_TEST_OUTPUT_LOW	BIT(1)
+#define TLMM_TEST_OUTPUT_HIGH	BIT(2)
+#define TLMM_TEST_THEN_HIGH	BIT(3)
+#define TLMM_TEST_THEN_LOW	BIT(4)
+#define TLMM_TEST_WAKE_THREAD	BIT(5)
+
+static void tlmm_output_low(void)
+{
+	writel(tlmm_suite.low_val, tlmm_suite.reg);
+	readl(tlmm_suite.reg);
+}
+
+static void tlmm_output_high(void)
+{
+	writel(tlmm_suite.high_val, tlmm_suite.reg);
+	readl(tlmm_suite.reg);
+}
+
+static irqreturn_t tlmm_test_intr_fn(int irq, void *dev_id)
+{
+	struct tlmm_test_priv *priv = dev_id;
+
+	if (priv->intr_op & TLMM_TEST_COUNT)
+		atomic_inc(&priv->intr_count);
+
+	if (priv->intr_op & TLMM_TEST_OUTPUT_LOW)
+		tlmm_output_low();
+	if (priv->intr_op & TLMM_TEST_OUTPUT_HIGH)
+		tlmm_output_high();
+
+	if (atomic_dec_if_positive(&priv->intr_op_remain) > 0) {
+		udelay(1);
+
+		if (priv->intr_op & TLMM_TEST_THEN_LOW)
+			tlmm_output_low();
+		if (priv->intr_op & TLMM_TEST_THEN_HIGH)
+			tlmm_output_high();
+	}
+
+	return priv->intr_op & TLMM_TEST_WAKE_THREAD ? IRQ_WAKE_THREAD : IRQ_HANDLED;
+}
+
+static irqreturn_t tlmm_test_intr_thread_fn(int irq, void *dev_id)
+{
+	struct tlmm_test_priv *priv = dev_id;
+
+	if (priv->thread_op & TLMM_TEST_COUNT)
+		atomic_inc(&priv->thread_count);
+
+	if (priv->thread_op & TLMM_TEST_OUTPUT_LOW)
+		tlmm_output_low();
+	if (priv->thread_op & TLMM_TEST_OUTPUT_HIGH)
+		tlmm_output_high();
+
+	if (atomic_dec_if_positive(&priv->thread_op_remain) > 0) {
+		udelay(1);
+		if (priv->thread_op & TLMM_TEST_THEN_LOW)
+			tlmm_output_low();
+		if (priv->thread_op & TLMM_TEST_THEN_HIGH)
+			tlmm_output_high();
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void tlmm_test_request_hard_irq(struct kunit *test, unsigned long irqflags)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	int ret;
+
+	ret = request_irq(tlmm_suite.irq, tlmm_test_intr_fn, irqflags, test->name, priv);
+	KUNIT_EXPECT_EQ(test, ret, 0);
+}
+
+static void tlmm_test_request_threaded_irq(struct kunit *test, unsigned long irqflags)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	int ret;
+
+	ret = request_threaded_irq(tlmm_suite.irq,
+				   tlmm_test_intr_fn, tlmm_test_intr_thread_fn,
+				   irqflags, test->name, priv);
+
+	KUNIT_EXPECT_EQ(test, ret, 0);
+}
+
+static void tlmm_test_silent(struct kunit *test, unsigned long irqflags)
+{
+	struct tlmm_test_priv *priv = test->priv;
+
+	priv->intr_op = TLMM_TEST_COUNT;
+
+	/* GPIO line at non-triggering level */
+	if (irqflags == IRQF_TRIGGER_LOW || irqflags == IRQF_TRIGGER_FALLING)
+		tlmm_output_high();
+	else
+		tlmm_output_low();
+
+	tlmm_test_request_hard_irq(test, irqflags);
+	msleep(100);
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 0);
+}
+
+/*
+ * Test that no RISING interrupts are triggered on a silent pin
+ */
+static void tlmm_test_silent_rising(struct kunit *test)
+{
+	tlmm_test_silent(test, IRQF_TRIGGER_RISING);
+}
+
+/*
+ * Test that no FALLING interrupts are triggered on a silent pin
+ */
+static void tlmm_test_silent_falling(struct kunit *test)
+{
+	tlmm_test_silent(test, IRQF_TRIGGER_FALLING);
+}
+
+/*
+ * Test that no LOW interrupts are triggered on a silent pin
+ */
+static void tlmm_test_silent_low(struct kunit *test)
+{
+	tlmm_test_silent(test, IRQF_TRIGGER_LOW);
+}
+
+/*
+ * Test that no HIGH interrupts are triggered on a silent pin
+ */
+static void tlmm_test_silent_high(struct kunit *test)
+{
+	tlmm_test_silent(test, IRQF_TRIGGER_HIGH);
+}
+
+/*
+ * Square wave with 10 high pulses, assert that we get 10 rising interrupts
+ */
+static void tlmm_test_rising(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	int i;
+
+	priv->intr_op = TLMM_TEST_COUNT;
+
+	tlmm_output_low();
+
+	tlmm_test_request_hard_irq(test, IRQF_TRIGGER_RISING);
+	for (i = 0; i < 10; i++) {
+		tlmm_output_low();
+		msleep(20);
+		tlmm_output_high();
+		msleep(20);
+	}
+
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+}
+
+/*
+ * Square wave with 10 low pulses, assert that we get 10 falling interrupts
+ */
+static void tlmm_test_falling(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	int i;
+
+	priv->intr_op = TLMM_TEST_COUNT;
+
+	tlmm_output_high();
+
+	tlmm_test_request_hard_irq(test, IRQF_TRIGGER_FALLING);
+	for (i = 0; i < 10; i++) {
+		tlmm_output_high();
+		msleep(20);
+		tlmm_output_low();
+		msleep(20);
+	}
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+}
+
+/*
+ * Drive line low 10 times, handler drives it high to "clear the interrupt
+ * source", assert we get 10 interrupts
+ */
+static void tlmm_test_low(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	int i;
+
+	priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH;
+	atomic_set(&priv->intr_op_remain, 9);
+
+	tlmm_output_high();
+
+	tlmm_test_request_hard_irq(test, IRQF_TRIGGER_LOW);
+	for (i = 0; i < 10; i++) {
+		msleep(20);
+		tlmm_output_low();
+	}
+	msleep(100);
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+}
+
+/*
+ * Drive line high 10 times, handler drives it low to "clear the interrupt
+ * source", assert we get 10 interrupts
+ */
+static void tlmm_test_high(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	int i;
+
+	priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW;
+	atomic_set(&priv->intr_op_remain, 9);
+
+	tlmm_output_low();
+
+	tlmm_test_request_hard_irq(test, IRQF_TRIGGER_HIGH);
+	for (i = 0; i < 10; i++) {
+		msleep(20);
+		tlmm_output_high();
+	}
+	msleep(100);
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+}
+
+/*
+ * Handler drives GPIO high to "clear the interrupt source", then low to
+ * simulate a new interrupt, repeated 10 times, assert we get 10 interrupts
+ */
+static void tlmm_test_falling_in_handler(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+
+	priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH | TLMM_TEST_THEN_LOW;
+	atomic_set(&priv->intr_op_remain, 10);
+
+	tlmm_output_high();
+
+	tlmm_test_request_hard_irq(test, IRQF_TRIGGER_FALLING);
+	msleep(20);
+	tlmm_output_low();
+	msleep(100);
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+}
+
+/*
+ * Handler drives GPIO low to "clear the interrupt source", then high to
+ * simulate a new interrupt, repeated 10 times, assert we get 10 interrupts
+ */
+static void tlmm_test_rising_in_handler(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+
+	priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW | TLMM_TEST_THEN_HIGH;
+	atomic_set(&priv->intr_op_remain, 10);
+
+	tlmm_output_low();
+
+	tlmm_test_request_hard_irq(test, IRQF_TRIGGER_RISING);
+	msleep(20);
+	tlmm_output_high();
+	msleep(100);
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+}
+
+/*
+ * Square wave with 10 high pulses, assert that we get 10 rising hard and
+ * 10 threaded interrupts
+ */
+static void tlmm_test_thread_rising(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	int i;
+
+	priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_WAKE_THREAD;
+	priv->thread_op = TLMM_TEST_COUNT;
+
+	tlmm_output_low();
+
+	tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_RISING);
+	for (i = 0; i < 10; i++) {
+		tlmm_output_low();
+		msleep(20);
+		tlmm_output_high();
+		msleep(20);
+	}
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10);
+}
+
+/*
+ * Square wave with 10 low pulses, assert that we get 10 falling interrupts
+ */
+static void tlmm_test_thread_falling(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	int i;
+
+	priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_WAKE_THREAD;
+	priv->thread_op = TLMM_TEST_COUNT;
+
+	tlmm_output_high();
+
+	tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_FALLING);
+	for (i = 0; i < 10; i++) {
+		tlmm_output_high();
+		msleep(20);
+		tlmm_output_low();
+		msleep(20);
+	}
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10);
+}
+
+/*
+ * Drive line high 10 times, threaded handler drives it low to "clear the
+ * interrupt source", assert we get 10 interrupts
+ */
+static void tlmm_test_thread_high(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	int i;
+
+	priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_WAKE_THREAD;
+	priv->thread_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW;
+
+	tlmm_output_low();
+
+	tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_HIGH | IRQF_ONESHOT);
+	for (i = 0; i < 10; i++) {
+		tlmm_output_high();
+		msleep(20);
+	}
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10);
+}
+
+/*
+ * Drive line low 10 times, threaded handler drives it high to "clear the
+ * interrupt source", assert we get 10 interrupts
+ */
+static void tlmm_test_thread_low(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	int i;
+
+	priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_WAKE_THREAD;
+	priv->thread_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH;
+
+	tlmm_output_high();
+
+	tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_LOW | IRQF_ONESHOT);
+	for (i = 0; i < 10; i++) {
+		tlmm_output_low();
+		msleep(20);
+	}
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10);
+}
+
+/*
+ * Handler drives GPIO low to "clear the interrupt source", then high in the
+ * threaded handler to simulate a new interrupt, repeated 10 times, assert we
+ * get 10 interrupts
+ */
+static void tlmm_test_thread_rising_in_handler(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+
+	priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_LOW | TLMM_TEST_WAKE_THREAD;
+	priv->thread_op = TLMM_TEST_COUNT | TLMM_TEST_THEN_HIGH;
+	atomic_set(&priv->thread_op_remain, 10);
+
+	tlmm_output_low();
+
+	tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_RISING);
+	msleep(20);
+	tlmm_output_high();
+	msleep(100);
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10);
+}
+
+/*
+ * Handler drives GPIO high to "clear the interrupt source", then low in the
+ * threaded handler to simulate a new interrupt, repeated 10 times, assert we
+ * get 10 interrupts
+ */
+static void tlmm_test_thread_falling_in_handler(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+
+	priv->intr_op = TLMM_TEST_COUNT | TLMM_TEST_OUTPUT_HIGH | TLMM_TEST_WAKE_THREAD;
+	priv->thread_op = TLMM_TEST_COUNT | TLMM_TEST_THEN_LOW;
+	atomic_set(&priv->thread_op_remain, 10);
+
+	tlmm_output_high();
+
+	tlmm_test_request_threaded_irq(test, IRQF_TRIGGER_FALLING);
+	msleep(20);
+	tlmm_output_low();
+	msleep(100);
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 10);
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->thread_count), 10);
+}
+
+/*
+ * Validate that edge interrupts occurring while irq is disabled is delivered
+ * once the interrupt is reenabled.
+ */
+static void tlmm_test_rising_while_disabled(struct kunit *test)
+{
+	struct tlmm_test_priv *priv = test->priv;
+	unsigned int after_edge;
+	unsigned int before_edge;
+
+	priv->intr_op = TLMM_TEST_COUNT;
+	atomic_set(&priv->thread_op_remain, 10);
+
+	tlmm_output_low();
+
+	tlmm_test_request_hard_irq(test, IRQF_TRIGGER_RISING);
+	msleep(20);
+
+	disable_irq(tlmm_suite.irq);
+	before_edge = atomic_read(&priv->intr_count);
+
+	tlmm_output_high();
+	msleep(20);
+	after_edge = atomic_read(&priv->intr_count);
+
+	msleep(20);
+	enable_irq(tlmm_suite.irq);
+	msleep(20);
+
+	free_irq(tlmm_suite.irq, priv);
+
+	KUNIT_ASSERT_EQ(test, before_edge, 0);
+	KUNIT_ASSERT_EQ(test, after_edge, 0);
+	KUNIT_ASSERT_EQ(test, atomic_read(&priv->intr_count), 1);
+}
+
+static int tlmm_test_init(struct kunit *test)
+{
+	struct tlmm_test_priv *priv;
+
+	priv = kunit_kzalloc(test, sizeof(*priv), GFP_KERNEL);
+
+	atomic_set(&priv->intr_count, 0);
+	atomic_set(&priv->thread_count, 0);
+
+	atomic_set(&priv->intr_op_remain, 0);
+	atomic_set(&priv->thread_op_remain, 0);
+
+	test->priv = priv;
+
+	return 0;
+}
+
+/*
+ * NOTE: When adding compatibles to this list, ensure that TLMM_REG_SIZE and
+ * pull configuration values are supported and correct.
+ */
+static const struct of_device_id tlmm_of_match[] = {
+	{ .compatible = "qcom,sc8280xp-tlmm" },
+	{ .compatible = "qcom,x1e80100-tlmm" },
+	{}
+};
+
+static int tlmm_test_init_suite(struct kunit_suite *suite)
+{
+	struct of_phandle_args args = {};
+	struct resource res;
+	int ret;
+	u32 val;
+
+	if (tlmm_test_gpio < 0) {
+		pr_err("use the tlmm-test.gpio module parameter to specify which GPIO to use\n");
+		return -EINVAL;
+	}
+
+	struct device_node *tlmm __free(device_node) = of_find_matching_node(NULL, tlmm_of_match);
+	if (!tlmm) {
+		pr_err("failed to find tlmm node\n");
+		return -EINVAL;
+	}
+
+	ret = of_address_to_resource(tlmm, 0, &res);
+	if (ret < 0)
+		return ret;
+
+	tlmm_suite.base = ioremap(res.start, resource_size(&res));
+	if (!tlmm_suite.base)
+		return -ENOMEM;
+
+	args.np = tlmm;
+	args.args_count = 2;
+	args.args[0] = tlmm_test_gpio;
+	args.args[1] = 0;
+
+	tlmm_suite.irq = irq_create_of_mapping(&args);
+	if (!tlmm_suite.irq) {
+		pr_err("failed to map TLMM irq %d\n", args.args[0]);
+		goto err_unmap;
+	}
+
+	tlmm_suite.reg = tlmm_suite.base + tlmm_test_gpio * TLMM_REG_SIZE;
+	val = readl(tlmm_suite.reg) & ~MSM_PULL_MASK;
+	tlmm_suite.low_val = val | MSM_PULL_DOWN;
+	tlmm_suite.high_val = val | MSM_PULL_UP;
+
+	return 0;
+
+err_unmap:
+	iounmap(tlmm_suite.base);
+	tlmm_suite.base = NULL;
+	return -EINVAL;
+}
+
+static void tlmm_test_exit_suite(struct kunit_suite *suite)
+{
+	irq_dispose_mapping(tlmm_suite.irq);
+	iounmap(tlmm_suite.base);
+
+	tlmm_suite.base = NULL;
+	tlmm_suite.irq = -1;
+}
+
+static struct kunit_case tlmm_test_cases[] = {
+	KUNIT_CASE(tlmm_test_silent_rising),
+	KUNIT_CASE(tlmm_test_silent_falling),
+	KUNIT_CASE(tlmm_test_silent_low),
+	KUNIT_CASE(tlmm_test_silent_high),
+	KUNIT_CASE(tlmm_test_rising),
+	KUNIT_CASE(tlmm_test_falling),
+	KUNIT_CASE(tlmm_test_high),
+	KUNIT_CASE(tlmm_test_low),
+	KUNIT_CASE(tlmm_test_rising_in_handler),
+	KUNIT_CASE(tlmm_test_falling_in_handler),
+	KUNIT_CASE(tlmm_test_thread_rising),
+	KUNIT_CASE(tlmm_test_thread_falling),
+	KUNIT_CASE(tlmm_test_thread_high),
+	KUNIT_CASE(tlmm_test_thread_low),
+	KUNIT_CASE(tlmm_test_thread_rising_in_handler),
+	KUNIT_CASE(tlmm_test_thread_falling_in_handler),
+	KUNIT_CASE(tlmm_test_rising_while_disabled),
+	{}
+};
+
+static struct kunit_suite tlmm_test_suite = {
+	.name = "tlmm-test",
+	.init = tlmm_test_init,
+	.suite_init = tlmm_test_init_suite,
+	.suite_exit = tlmm_test_exit_suite,
+	.test_cases = tlmm_test_cases,
+};
+
+kunit_test_suites(&tlmm_test_suite);
+
+MODULE_DESCRIPTION("Qualcomm TLMM test");
+MODULE_LICENSE("GPL");