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| author | André Draszik <andre.draszik@linaro.org> | 2025-10-06 09:07:12 +0100 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2025-11-20 22:10:17 +0530 |
| commit | 5e428e45bf17a8f3784099ca5ded16e3b5d59766 (patch) | |
| tree | e45a0b0d2cacf7464a14fffd88fb60fb1235c5fc /drivers/phy | |
| parent | 356d1924b9a6bc2164ce2bf1fad147b0c37ae085 (diff) | |
| download | linux-next-5e428e45bf17a8f3784099ca5ded16e3b5d59766.tar.gz linux-next-5e428e45bf17a8f3784099ca5ded16e3b5d59766.zip | |
phy: exynos5-usbdrd: fix clock prepare imbalance
Commit f4fb9c4d7f94 ("phy: exynos5-usbdrd: allow DWC3 runtime suspend
with UDC bound (E850+)") incorrectly added clk_bulk_disable() as the
inverse of clk_bulk_prepare_enable() while it should have of course
used clk_bulk_disable_unprepare(). This means incorrect reference
counts to the CMU driver remain.
Update the code accordingly.
Fixes: f4fb9c4d7f94 ("phy: exynos5-usbdrd: allow DWC3 runtime suspend with UDC bound (E850+)")
CC: stable@vger.kernel.org
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20251006-gs101-usb-phy-clk-imbalance-v1-1-205b206126cf@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'drivers/phy')
| -rw-r--r-- | drivers/phy/samsung/phy-exynos5-usbdrd.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung/phy-exynos5-usbdrd.c index a88ba95bdc8f..1c8bf80119f1 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -1823,7 +1823,7 @@ static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw, phy_drd->orientation = orientation; } - clk_bulk_disable(phy_drd->drv_data->n_clks, phy_drd->clks); + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); return 0; } |