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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2026-08-20 14:53:54 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2026-08-20 14:53:54 -0700 |
| commit | 073e62fd33fe9cec754cb89e60c0ebbab781a50a (patch) | |
| tree | 796305cc43819b294ef8877eb7bdb0d27fe567bd /drivers/perf | |
| parent | 73cc4da3857bb2970b3e349ed9608ca37861a84e (diff) | |
| parent | 8da45c93dfa98f25b148512d92ecfa75d027a5cc (diff) | |
| download | linux-next-073e62fd33fe9cec754cb89e60c0ebbab781a50a.tar.gz linux-next-073e62fd33fe9cec754cb89e60c0ebbab781a50a.zip | |
Merge tag 'riscv-for-linus-7.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Paul Walmsley
- Add initial definitions and discovery for the Smcsrind, Sscsrind,
Smcntrpmf, Ssccfg, Smcdeleg, Zicclsm, Ziccamoa, Ziccif, Ziccrse,
Za64rs, and Ssqosid RISC-V ISA extensions
- Improve the RISC-V update_mmu_cache_range() implementation by using
flush-by-ASID, enabling performance improvements on
microarchitectures that support related optimizations; and by taking
advantage of the Svinval RISC-V ISA extension on microarchitectures
that support it
- Shrink CFI shadow stack allocation further (to 512MB) to save virtual
address space (and physical memory on systems with strict overcommit
policies)
- Add initial CPU context switch support for QoS tagging (Ssqosid)
- Change our vector misaligned access speed test code to be
synchronous, avoiding a bunch of bugs related to unnecessary
asynchronicity
- Enable ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V to help with ACPI table
debugging (similar to ARM64 and x86)
- Extract vDSO section offsets at build time, rather than run time, to
avoid the boot time overhead
- Use assembler directives to control the use of instructions from the
RISC-V ISA extensions Zacas and Zabha, rather than compiler -march
flags that could affect the whole kernel (similar to ARM64)
- Add a kselftest for kprobes support for the c.jal instruction on
RISC-V
- When UEFI runtime services are available, use them to restart and
power off
- Fix ARCH_HAS_ACPI_TABLE_UPGRADE for RISC-V by adding a missing
include file to the ACPI code
- Move contiguous DMA memory reservation later in the boot, to ensure
that the correct global and per-node pools are allocated when
CONFIG_CMA_SIZE_PERNUMA is enabled
- Disallow probes on breakpoint handlers to avoid recursing
indefinitely into do_trap_break()
- Patch the compat vDSO during runtime alternatives processing, not
only the standard vDSO
- Remove some leftover XIP support elements missed by commit
9b3a2be84803 ("riscv: Remove support for XIP kernel")
- Fix broadcast timer switching in ACPI LPI power states by
implementing a RISC-V version of arch_get_idle_state_flags()
- Miscellaneous fixes, including: vDSO makefile simplification; marking
our default_power_off() as __noreturn; error path fixes in the PMU
SBI perf driver; RISC-V extension capitalization consistency; the use
of BIT() macros in one of our include files; and some documentation
fixes
* tag 'riscv-for-linus-7.3-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (39 commits)
RISC-V: hwprobe: Use BIT macro to avoid warnings
riscv: alternative: Also patch the compat vDSO
riscv: alternative: Use the statically extracted vDSO section offsets
riscv: vdso: Add symbols for the alternative section boundaries
riscv: Add Ziccamoa, Ziccif, Ziccrse, and Za64rs to cpufeature and hwprobe
riscv: Add Zicclsm to cpufeature and hwprobe
riscv: cpufeature: Clarify ISA spec version for canonical order
riscv: Standardize extension capitalization
riscv: kprobes: Prevent probes in breakpoint handlers
riscv: cmpxchg: Use .option arch for Zacas and Zabha
riscv: acpi: Handle LPI architectural context loss flags
riscv: further remove XIP
riscv: Add support for srmcfg CSR from Ssqosid extension
riscv: Detect the Ssqosid extension
dt-bindings: riscv: Add Ssqosid extension description
dt-bindings: riscv: add Counter delegation ISA extensions description
RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing
RISC-V: Add Ssccfg extension CSR definition
dt-bindings: riscv: add Smcntrpmf ISA extension description
RISC-V: Add Smcntrpmf extension parsing
...
Diffstat (limited to 'drivers/perf')
| -rw-r--r-- | drivers/perf/riscv_pmu_sbi.c | 33 |
1 files changed, 27 insertions, 6 deletions
diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index dfc886dee5ad..50220f7b46d9 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -1219,22 +1219,29 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde DOMAIN_BUS_ANY); if (!domain) { pr_err("Failed to find INTC IRQ root domain\n"); - return -ENODEV; + ret = -ENODEV; + goto err; } riscv_pmu_irq = irq_create_mapping(domain, riscv_pmu_irq_num); if (!riscv_pmu_irq) { pr_err("Failed to map PMU interrupt for node\n"); - return -ENODEV; + ret = -ENODEV; + goto err; } ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events); if (ret) { pr_err("registering percpu irq failed [%d]\n", ret); - return ret; + irq_dispose_mapping(riscv_pmu_irq); + riscv_pmu_irq = 0; + goto err; } return 0; +err: + riscv_pmu_use_irq = false; + return ret; } #ifdef CONFIG_CPU_PM @@ -1301,7 +1308,8 @@ static void riscv_pmu_destroy(struct riscv_pmu *pmu) } } riscv_pm_pmu_unregister(pmu); - cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); + if (!hlist_unhashed(&pmu->node)) + cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); } static void pmu_sbi_event_init(struct perf_event *event) @@ -1423,6 +1431,7 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) struct riscv_pmu *pmu = NULL; int ret = -ENODEV; int num_counters; + bool irq_requested = false; pr_info("SBI PMU extension is available\n"); pmu = riscv_pmu_alloc(); @@ -1451,6 +1460,7 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE; } + irq_requested = (ret == 0); pmu->pmu.attr_groups = riscv_pmu_attr_groups; pmu->pmu.parent = &pdev->dev; @@ -1469,11 +1479,11 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) ret = riscv_pm_pmu_register(pmu); if (ret) - goto out_unregister; + goto out_destroy; ret = perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW); if (ret) - goto out_unregister; + goto out_destroy; /* SBI PMU Snapsphot is only available in SBI v2.0 */ if (sbi_v2_available) { @@ -1514,9 +1524,20 @@ static int pmu_sbi_device_probe(struct platform_device *pdev) return 0; out_unregister: + perf_pmu_unregister(&pmu->pmu); + +out_destroy: riscv_pmu_destroy(pmu); + if (irq_requested) { + free_percpu_irq(riscv_pmu_irq, pmu->hw_events); + irq_dispose_mapping(riscv_pmu_irq); + riscv_pmu_irq = 0; + } out_free: + free_percpu(pmu->hw_events); + kfree(pmu_ctr_list); + pmu_ctr_list = NULL; kfree(pmu); return ret; } |
