Merge branch 'pci/controller/tlp_macros'

- Add common TLP Type macros (MRd/Wr, IORd/Wr, CfgRd/Wr 0, CfgRd/Wr 1, Msg)
  and use them in aspeed, cadence, dwc, mediatek, tegra drivers (Hans
  Zhang)

* pci/controller/tlp_macros:
  PCI: cadence: Use common TLP type macros
  PCI: dwc: Replace ATU type macros with common TLP type macros
  PCI: Add common TLP type macros and convert aspeed/mediatek

9 files changed, 34 insertions, 40 deletions

diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h
index 026e131600de..72299121fd44 100644
--- a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h
+++ b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h
@@ -14,6 +14,8 @@
 #include <linux/phy/phy.h>
 #include <linux/bitfield.h>
 
+#include "../../pci.h"
+
 /* High Performance Architecture (HPA) PCIe controller registers */
 #define CDNS_PCIE_HPA_IP_REG_BANK		0x01000000
 #define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK	0x01003C00
@@ -119,15 +121,15 @@
 #define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r)                (0x1008 + ((r) & 0x1F) * 0x0080)
 #define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK         GENMASK(28, 24)
 #define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM  \
-	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0)
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, PCIE_TLP_TYPE_MEM_RDWR)
 #define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO   \
-	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2)
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, PCIE_TLP_TYPE_IO_RDWR)
 #define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0  \
-	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4)
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, PCIE_TLP_TYPE_CFG0_RDWR)
 #define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1  \
-	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5)
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, PCIE_TLP_TYPE_CFG1_RDWR)
 #define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG  \
-	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10)
+	FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, PCIE_TLP_TYPE_MSG)
 
 /* Region r Outbound PCIe Descriptor Register */
 #define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r)        (0x100C + ((r) & 0x1F) * 0x0080)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index e4c6f7193495..5faae6ce73ef 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -585,9 +585,9 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 
 config_atu:
 	if (!(flags & PCI_BASE_ADDRESS_SPACE))
-		type = PCIE_ATU_TYPE_MEM;
+		type = PCIE_TLP_TYPE_MEM_RDWR;
 	else
-		type = PCIE_ATU_TYPE_IO;
+		type = PCIE_TLP_TYPE_IO_RDWR;
 
 	if (epf_bar->num_submap)
 		ret = dw_pcie_ep_ib_atu_addr(ep, func_no, type, epf_bar);
@@ -660,7 +660,7 @@ static int dw_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no, u8 vfunc_no,
 	struct dw_pcie_ob_atu_cfg atu = { 0 };
 
 	atu.func_no = func_no;
-	atu.type = PCIE_ATU_TYPE_MEM;
+	atu.type = PCIE_TLP_TYPE_MEM_RDWR;
 	atu.parent_bus_addr = addr - pci->parent_bus_offset;
 	atu.pci_addr = pci_addr;
 	atu.size = size;
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 2a467ed14aa8..06722259d2e3 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -436,7 +436,7 @@ static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp)
 	 * remaining buses need type 1 iATU configuration.
 	 */
 	atu.index = 0;
-	atu.type = PCIE_ATU_TYPE_CFG0;
+	atu.type = PCIE_TLP_TYPE_CFG0_RDWR;
 	atu.parent_bus_addr = pp->cfg0_base + SZ_1M;
 	/* 1MiB is to cover 1 (bus) * 32 (devices) * 8 (functions) */
 	atu.size = SZ_1M;
@@ -452,7 +452,7 @@ static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp)
 
 	/* Configure remaining buses in type 1 iATU configuration */
 	atu.index = 1;
-	atu.type = PCIE_ATU_TYPE_CFG1;
+	atu.type = PCIE_TLP_TYPE_CFG1_RDWR;
 	atu.parent_bus_addr = pp->cfg0_base + SZ_2M;
 	atu.size = (SZ_1M * bus_range_max) - SZ_2M;
 	atu.ctrl2 = PCIE_ATU_CFG_SHIFT_MODE_ENABLE;
@@ -749,9 +749,9 @@ static void __iomem *dw_pcie_other_conf_map_bus(struct pci_bus *bus,
 		 PCIE_ATU_FUNC(PCI_FUNC(devfn));
 
 	if (pci_is_root_bus(bus->parent))
-		type = PCIE_ATU_TYPE_CFG0;
+		type = PCIE_TLP_TYPE_CFG0_RDWR;
 	else
-		type = PCIE_ATU_TYPE_CFG1;
+		type = PCIE_TLP_TYPE_CFG1_RDWR;
 
 	atu.type = type;
 	atu.parent_bus_addr = pp->cfg0_base - pci->parent_bus_offset;
@@ -778,7 +778,7 @@ static int dw_pcie_rd_other_conf(struct pci_bus *bus, unsigned int devfn,
 		return ret;
 
 	if (pp->cfg0_io_shared) {
-		atu.type = PCIE_ATU_TYPE_IO;
+		atu.type = PCIE_TLP_TYPE_IO_RDWR;
 		atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset;
 		atu.pci_addr = pp->io_bus_addr;
 		atu.size = pp->io_size;
@@ -804,7 +804,7 @@ static int dw_pcie_wr_other_conf(struct pci_bus *bus, unsigned int devfn,
 		return ret;
 
 	if (pp->cfg0_io_shared) {
-		atu.type = PCIE_ATU_TYPE_IO;
+		atu.type = PCIE_TLP_TYPE_IO_RDWR;
 		atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset;
 		atu.pci_addr = pp->io_bus_addr;
 		atu.size = pp->io_size;
@@ -912,7 +912,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 		if (resource_type(entry->res) != IORESOURCE_MEM)
 			continue;
 
-		atu.type = PCIE_ATU_TYPE_MEM;
+		atu.type = PCIE_TLP_TYPE_MEM_RDWR;
 		atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset;
 		atu.pci_addr = entry->res->start - entry->offset;
 
@@ -955,7 +955,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 	if (pp->io_size) {
 		if (ob_iatu_index < pci->num_ob_windows) {
 			atu.index = ob_iatu_index;
-			atu.type = PCIE_ATU_TYPE_IO;
+			atu.type = PCIE_TLP_TYPE_IO_RDWR;
 			atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset;
 			atu.pci_addr = pp->io_bus_addr;
 			atu.size = pp->io_size;
@@ -1017,7 +1017,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 
 			window_size = MIN(pci->region_limit + 1, res_size);
 			ret = dw_pcie_prog_inbound_atu(pci, ib_iatu_index,
-						       PCIE_ATU_TYPE_MEM, res_start,
+						       PCIE_TLP_TYPE_MEM_RDWR, res_start,
 						       res_start - entry->offset, window_size);
 			if (ret) {
 				dev_err(pci->dev, "Failed to set DMA range %pr\n",
@@ -1198,7 +1198,7 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci)
 
 	atu.code = PCIE_MSG_CODE_PME_TURN_OFF;
 	atu.routing = PCIE_MSG_TYPE_R_BC;
-	atu.type = PCIE_ATU_TYPE_MSG;
+	atu.type = PCIE_TLP_TYPE_MSG;
 	atu.size = resource_size(pci->pp.msg_res);
 	atu.index = pci->pp.msg_atu_index;
 
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 828bbf1e8e72..a9421fd3455b 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -573,7 +573,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 	dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val);
 
 	val = PCIE_ATU_ENABLE | atu->ctrl2;
-	if (atu->type == PCIE_ATU_TYPE_MSG) {
+	if (atu->type == PCIE_TLP_TYPE_MSG) {
 		/* The data-less messages only for now */
 		val |= PCIE_ATU_INHIBIT_PAYLOAD | atu->code;
 	}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 7dac37521b8e..de4b245b1758 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -195,11 +195,6 @@
 #define PCIE_ATU_VIEWPORT_SIZE		0x2C
 #define PCIE_ATU_REGION_CTRL1		0x000
 #define PCIE_ATU_INCREASE_REGION_SIZE	BIT(13)
-#define PCIE_ATU_TYPE_MEM		0x0
-#define PCIE_ATU_TYPE_IO		0x2
-#define PCIE_ATU_TYPE_CFG0		0x4
-#define PCIE_ATU_TYPE_CFG1		0x5
-#define PCIE_ATU_TYPE_MSG		0x10
 #define PCIE_ATU_TD			BIT(8)
 #define PCIE_ATU_FUNC_NUM(pf)           ((pf) << 20)
 #define PCIE_ATU_REGION_CTRL2		0x004
diff --git a/drivers/pci/controller/dwc/pcie-tegra194-acpi.c b/drivers/pci/controller/dwc/pcie-tegra194-acpi.c
index 55f61914a986..2d737b49ea8f 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194-acpi.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194-acpi.c
@@ -86,11 +86,11 @@ static void __iomem *tegra194_map_bus(struct pci_bus *bus,
 
 	if (bus->parent->number == cfg->busr.start) {
 		if (PCI_SLOT(devfn) == 0)
-			type = PCIE_ATU_TYPE_CFG0;
+			type = PCIE_TLP_TYPE_CFG0_RDWR;
 		else
 			return NULL;
 	} else {
-		type = PCIE_ATU_TYPE_CFG1;
+		type = PCIE_TLP_TYPE_CFG1_RDWR;
 	}
 
 	program_outbound_atu(pcie_ecam, 0, type, cfg->res.start, busdev,
diff --git a/drivers/pci/controller/pcie-aspeed.c b/drivers/pci/controller/pcie-aspeed.c
index 6acfae7d026e..9aa9e14c6148 100644
--- a/drivers/pci/controller/pcie-aspeed.c
+++ b/drivers/pci/controller/pcie-aspeed.c
@@ -127,19 +127,19 @@
 #define CFG0_READ_FMTTYPE                                        \
 	FIELD_PREP(ASPEED_TLP_COMMON_FIELDS,                     \
 		   ASPEED_TLP_FMT_TYPE(PCIE_TLP_FMT_3DW_NO_DATA, \
-				       PCIE_TLP_TYPE_CFG0_RD))
+				       PCIE_TLP_TYPE_CFG0_RDWR))
 #define CFG0_WRITE_FMTTYPE                                    \
 	FIELD_PREP(ASPEED_TLP_COMMON_FIELDS,                  \
 		   ASPEED_TLP_FMT_TYPE(PCIE_TLP_FMT_3DW_DATA, \
-				       PCIE_TLP_TYPE_CFG0_WR))
+				       PCIE_TLP_TYPE_CFG0_RDWR))
 #define CFG1_READ_FMTTYPE                                        \
 	FIELD_PREP(ASPEED_TLP_COMMON_FIELDS,                     \
 		   ASPEED_TLP_FMT_TYPE(PCIE_TLP_FMT_3DW_NO_DATA, \
-				       PCIE_TLP_TYPE_CFG1_RD))
+				       PCIE_TLP_TYPE_CFG1_RDWR))
 #define CFG1_WRITE_FMTTYPE                                    \
 	FIELD_PREP(ASPEED_TLP_COMMON_FIELDS,                  \
 		   ASPEED_TLP_FMT_TYPE(PCIE_TLP_FMT_3DW_DATA, \
-				       PCIE_TLP_TYPE_CFG1_WR))
+				       PCIE_TLP_TYPE_CFG1_RDWR))
 #define CFG_PAYLOAD_SIZE		0x01 /* 1 DWORD */
 #define TLP_HEADER_BYTE_EN(x, y)	((GENMASK((x) - 1, 0) << ((y) % 4)))
 #define TLP_GET_VALUE(x, y, z)	\
diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index afb0e4cc7974..8b57c3d75b94 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -112,10 +112,6 @@
 #define APP_CFG_REQ		BIT(0)
 #define APP_CPL_STATUS		GENMASK(7, 5)
 
-#define CFG_WRRD_TYPE_0		4
-#define CFG_WR_FMT		2
-#define CFG_RD_FMT		0
-
 #define CFG_DW0_LENGTH(length)	((length) & GENMASK(9, 0))
 #define CFG_DW0_TYPE(type)	(((type) << 24) & GENMASK(28, 24))
 #define CFG_DW0_FMT(fmt)	(((fmt) << 29) & GENMASK(31, 29))
@@ -298,7 +294,7 @@ static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
 	u32 tmp;
 
 	/* Write PCIe configuration transaction header for Cfgrd */
-	writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
+	writel(CFG_HEADER_DW0(PCIE_TLP_TYPE_CFG0_RDWR, PCIE_TLP_FMT_3DW_NO_DATA),
 	       port->base + PCIE_CFG_HEADER0);
 	writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
 	writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
@@ -328,7 +324,7 @@ static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
 			      int where, int size, u32 val)
 {
 	/* Write PCIe configuration transaction header for Cfgwr */
-	writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
+	writel(CFG_HEADER_DW0(PCIE_TLP_TYPE_CFG0_RDWR, PCIE_TLP_FMT_3DW_DATA),
 	       port->base + PCIE_CFG_HEADER0);
 	writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
 	writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index b36667969ad5..a6dcc32be16a 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -71,10 +71,11 @@ struct pcie_tlp_log;
 #define PCIE_TLP_FMT_4DW_DATA		0x03 /* 4DW header, with data */
 
 /* Type of TLP; PCIe r7.0, sec 2.2.1 */
-#define PCIE_TLP_TYPE_CFG0_RD		0x04 /* Config Type 0 Read Request */
-#define PCIE_TLP_TYPE_CFG0_WR		0x04 /* Config Type 0 Write Request */
-#define PCIE_TLP_TYPE_CFG1_RD		0x05 /* Config Type 1 Read Request */
-#define PCIE_TLP_TYPE_CFG1_WR		0x05 /* Config Type 1 Write Request */
+#define PCIE_TLP_TYPE_MEM_RDWR		0x00 /* Memory Read/Write Request */
+#define PCIE_TLP_TYPE_IO_RDWR		0x02 /* I/O Read/Write Request */
+#define PCIE_TLP_TYPE_CFG0_RDWR		0x04 /* Config Type 0 Read/Write Request */
+#define PCIE_TLP_TYPE_CFG1_RDWR		0x05 /* Config Type 1 Read/Write Request */
+#define PCIE_TLP_TYPE_MSG		0x10 /* Message With/Without data Request */
 
 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
 #define PCIE_MSG_TYPE_R_RC	0