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| author | Mohamad Raizudeen <raizudeen.kerneldev@gmail.com> | 2026-07-23 22:42:03 +0530 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2026-08-13 11:51:03 -0500 |
| commit | 23d7eed5974989de56273c964d7e510e4aad91e8 (patch) | |
| tree | 4d6532ff6954b04f1fc7dee34d756173d93beb1f /drivers/pci | |
| parent | 062fb7f816439da6bf3860386889343482a66bd4 (diff) | |
| download | linux-next-23d7eed5974989de56273c964d7e510e4aad91e8.tar.gz linux-next-23d7eed5974989de56273c964d7e510e4aad91e8.zip | |
PCI: Fix 32-bit config write in Intel PCH Root Port MPC ACS quirk
pci_quirk_enable_intel_rp_mpc_acs() reads a 32-bit DWORD from the MPC
register, sets bit 26 (INTEL_MPC_REG_IRBNCE), but it writes it back using
pci_write_config_word().
Because bit 26 resides in the upper 16 bits of the 32-bit register, a
16-bit write drops the newly set bit. The quirk logs that it is enabling
IRBNCE, but the hardware never actually receives the command.
Use pci_write_config_dword() to ensure the full 32-bit value is written
back to the hardware.
Fixes: d99321b63b1f ("PCI: Enable quirks for PCIe ACS on Intel PCH root ports")
Signed-off-by: Mohamad Raizudeen <raizudeen.kerneldev@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260723171203.4892-1-raizudeen.kerneldev@gmail.com
Diffstat (limited to 'drivers/pci')
| -rw-r--r-- | drivers/pci/quirks.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 27f7d56c9ac3..1dab1076f679 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -5361,7 +5361,7 @@ static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) if (!(mpc & INTEL_MPC_REG_IRBNCE)) { pci_info(dev, "Enabling MPC IRBNCE\n"); mpc |= INTEL_MPC_REG_IRBNCE; - pci_write_config_word(dev, INTEL_MPC_REG, mpc); + pci_write_config_dword(dev, INTEL_MPC_REG, mpc); } } |