diff options
| author | Hans Zhang <18255117159@163.com> | 2026-09-12 00:25:37 +0800 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> | 2026-09-28 05:06:36 +0200 |
| commit | 4996364a46e738cc455f5fa9b8b09f2f3348bcc9 (patch) | |
| tree | 5917d2191046203e640a3cfb7fa0df9e686aed40 /drivers/pci/controller/dwc | |
| parent | f29719b5064c07cec23c928055df302181374df5 (diff) | |
| download | linux-next-4996364a46e738cc455f5fa9b8b09f2f3348bcc9.tar.gz linux-next-4996364a46e738cc455f5fa9b8b09f2f3348bcc9.zip | |
PCI: dwc: Remove unused PCIE_ATU_UNR_* register definitions
The PCIE_ATU_UNR_* macros are not used anywhere in the kernel. They
were presumably intended for unrolled iATU register access, but the
driver now uses the ATU_* macros and computes unrolled offsets via
ATU_UNROLL_BASE().
Remove these unused definitions. No functional change intended.
Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Link: https://patch.msgid.link/20260911162537.469018-3-18255117159@163.com
Diffstat (limited to 'drivers/pci/controller/dwc')
| -rw-r--r-- | drivers/pci/controller/dwc/pcie-designware.h | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index aa79f000b160..aea474ad803c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -271,18 +271,6 @@ #define MARGINING_MAXLANES GENMASK(20, 16) #define MARGINING_SAMPLE_RATE_TIMING GENMASK(13, 8) #define MARGINING_SAMPLE_RATE_VOLTAGE GENMASK(5, 0) -/* - * iATU Unroll-specific register definitions - * From 4.80 core version the address translation will be made by unroll - */ -#define PCIE_ATU_UNR_REGION_CTRL1 0x00 -#define PCIE_ATU_UNR_REGION_CTRL2 0x04 -#define PCIE_ATU_UNR_LOWER_BASE 0x08 -#define PCIE_ATU_UNR_UPPER_BASE 0x0C -#define PCIE_ATU_UNR_LOWER_LIMIT 0x10 -#define PCIE_ATU_UNR_LOWER_TARGET 0x14 -#define PCIE_ATU_UNR_UPPER_TARGET 0x18 -#define PCIE_ATU_UNR_UPPER_LIMIT 0x20 /* * RAS-DES register definitions |