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| author | Gustavo Sousa <gustavo.sousa@intel.com> | 2026-03-09 21:42:12 -0300 |
|---|---|---|
| committer | Gustavo Sousa <gustavo.sousa@intel.com> | 2026-03-10 19:18:46 -0300 |
| commit | 68bed0d6bfae422b7297c62736fee0134b3b0c24 (patch) | |
| tree | ba66ba662373b33b217911a7dae191057dda5159 /drivers/gpu/drm | |
| parent | 44b512754d168b9ed7b8bc128565150203c9ac38 (diff) | |
| download | linux-next-68bed0d6bfae422b7297c62736fee0134b3b0c24.tar.gz linux-next-68bed0d6bfae422b7297c62736fee0134b3b0c24.zip | |
drm/xe: Translate C-state "reset value" into RC6
There are higher level sleep states that will cause RC6 state readout to
come back with an "in-reset" value. That is the case with NVL-P. As
those states are only possible if the GT is already in C6, let's just
translate the "reset value" into C6 when doing the readout.
Bspec: 67651
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patch.msgid.link/20260309-extra-nvl-p-enabling-patches-v5-7-be9c902ee34e@intel.com
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Diffstat (limited to 'drivers/gpu/drm')
| -rw-r--r-- | drivers/gpu/drm/xe/regs/xe_gt_regs.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_guc_pc.c | 8 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 7b927862f003..84b80e83ac46 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -20,6 +20,7 @@ #define MTL_MIRROR_TARGET_WP1 XE_REG(0xc60) #define MTL_CAGF_MASK REG_GENMASK(8, 0) #define MTL_CC_MASK REG_GENMASK(12, 9) +#define MTL_CRST 0xf /* RPM unit config (Gen8+) */ #define RPM_CONFIG0 XE_REG(0xd00) diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c index 21fe73ab4583..bb8c4e793492 100644 --- a/drivers/gpu/drm/xe/xe_guc_pc.c +++ b/drivers/gpu/drm/xe/xe_guc_pc.c @@ -756,6 +756,14 @@ enum xe_gt_idle_state xe_guc_pc_c_status(struct xe_guc_pc *pc) if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) { reg = xe_mmio_read32(>->mmio, MTL_MIRROR_TARGET_WP1); gt_c_state = REG_FIELD_GET(MTL_CC_MASK, reg); + + /* + * There are higher level sleep states that will cause this + * field to read out as its reset state, and those are only + * possible after the GT is already in C6. + */ + if (gt_c_state == MTL_CRST) + gt_c_state = GT_C6; } else { reg = xe_mmio_read32(>->mmio, GT_CORE_STATUS); gt_c_state = REG_FIELD_GET(RCN_MASK, reg); |