drm/xe/xe_ras: Add support to query device memory errors

Add initial support to query uncorrectable device memory errors from
system controller. The recovery action for memory errors depends on the
error category. Firmware will set only one error category per response.
Double bit ECC (Error Correcting Code) errors will be handled using Page
offlining in a later patch. Poison and data parity errors are only logged.
Rest of the errors require SBR (Secondary Bus Reset) to recover.

Cc: Tejas Upadhyay <tejas.upadhyay@intel.com>
Cc: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
Link: https://patch.msgid.link/20260717141650.2487761-8-riana.tauro@intel.com
Signed-off-by: Riana Tauro <riana.tauro@intel.com>

2 files changed, 53 insertions, 0 deletions

diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
index 73f9949286b4..a31e06b8aa67 100644
--- a/drivers/gpu/drm/xe/xe_ras.c
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -276,6 +276,36 @@ static u8 handle_soc_internal_errors(struct xe_device *xe, struct xe_ras_error_a
 	return XE_RAS_RECOVERY_ACTION_RESET;
 }
 
+static u8 handle_device_memory_errors(struct xe_device *xe, struct xe_ras_error_array *arr)
+{
+	struct xe_ras_memory_error *info = (void *)arr->details;
+
+	/*
+	 * For memory errors, the recovery action depends on the error category
+	 *
+	 * TODO: Double-bit ECC errors: Page offlining
+	 * Poison and data parity errors: Log only
+	 * For any other memory errors, request a reset as recovery mechanism
+	 */
+	switch (info->category) {
+	case XE_RAS_MEMORY_POISON:
+		xe_info(xe, "[RAS]: Poison error detected\n");
+		break;
+	case XE_RAS_MEMORY_DATA_PARITY:
+		xe_info(xe, "[RAS]: Data parity error detected\n");
+		break;
+	case XE_RAS_MEMORY_DB_ECC:
+		xe_info(xe, "[RAS]: Double-bit ECC error detected at sw address 0x%llx\n",
+			info->sw_address);
+		/* TODO: Add page offlining for Double-bit ECC error */
+		fallthrough;
+	default:
+		return XE_RAS_RECOVERY_ACTION_RESET;
+	}
+
+	return XE_RAS_RECOVERY_ACTION_RECOVERED;
+}
+
 void xe_ras_counter_threshold_crossed(struct xe_device *xe,
 				      struct xe_sysctrl_event_response *response)
 {
@@ -402,6 +432,9 @@ enum xe_ras_recovery_action xe_ras_process_errors(struct xe_device *xe)
 			case XE_RAS_COMP_SOC_INTERNAL:
 				action = handle_soc_internal_errors(xe, arr);
 				break;
+			case XE_RAS_COMP_DEVICE_MEMORY:
+				action = handle_device_memory_errors(xe, arr);
+				break;
 			default:
 				/* For any other component, reset */
 				action = XE_RAS_RECOVERY_ACTION_RESET;
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
index 066c1c39fc89..99b2466e2062 100644
--- a/drivers/gpu/drm/xe/xe_ras_types.h
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -12,6 +12,10 @@
 #define XE_RAS_NUM_ERROR_ARR			3
 /* Error bits in IEH global error status register */
 #define XE_RAS_SOC_IEH_PUNIT			BIT(1)
+/* Device memory error categories */
+#define XE_RAS_MEMORY_DB_ECC			BIT(1)
+#define XE_RAS_MEMORY_POISON			BIT(2)
+#define XE_RAS_MEMORY_DATA_PARITY		BIT(5)
 
 /**
  * enum xe_ras_recovery_action - RAS recovery actions
@@ -226,6 +230,22 @@ struct xe_ras_ieh_error {
 } __packed;
 
 /**
+ * struct xe_ras_memory_error - Device memory error details
+ */
+struct xe_ras_memory_error {
+	/** @category: Device memory error category */
+	u8 category;
+	/** @reserved: Reserved for future use */
+	u8 reserved[7];
+	/** @reserved1: Reserved for future use */
+	u64 reserved1;
+	/** @sw_address: Software address where error occurred */
+	u64 sw_address;
+	/** @reserved2: Reserved for future use */
+	u32 reserved2[10];
+} __packed;
+
+/**
  * struct xe_ras_get_health_request - Request structure for obtaining gpu health
  */
 struct xe_ras_get_health_request {