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| author | Suraj Kandpal <suraj.kandpal@intel.com> | 2025-11-01 08:55:10 +0530 |
|---|---|---|
| committer | Suraj Kandpal <suraj.kandpal@intel.com> | 2025-11-01 09:04:20 +0530 |
| commit | 89e0a91e89559cd316c3bf56f65e4e272e50c10d (patch) | |
| tree | 996f540d30b4b2ac2ef48a86544925be6d0d6388 /drivers/gpu/drm/i915/display/intel_ddi.c | |
| parent | 3a6f155ce09b09af49452cf000ee7924da5bc0a8 (diff) | |
| download | linux-next-89e0a91e89559cd316c3bf56f65e4e272e50c10d.tar.gz linux-next-89e0a91e89559cd316c3bf56f65e4e272e50c10d.zip | |
drm/i915/ltphy: Define function to readout LT Phy PLL state
Define a function to readout hw state for LT Phy PLL which
can be used in get_config function call.
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
Link: https://patch.msgid.link/20251101032513.4171255-23-suraj.kandpal@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_ddi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_ddi.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index e412e625b666..733ef4559131 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4246,6 +4246,19 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, &crtc_state->dpll_hw_state); } +static void xe3plpd_ddi_get_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state) +{ + intel_lt_phy_pll_readout_hw_state(encoder, crtc_state, &crtc_state->dpll_hw_state.ltpll); + + if (crtc_state->dpll_hw_state.ltpll.tbt_mode) + crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder); + else + crtc_state->port_clock = + intel_lt_phy_calc_port_clock(encoder, crtc_state); + intel_ddi_get_config(encoder, crtc_state); +} + static void mtl_ddi_get_config(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state) { @@ -5241,6 +5254,7 @@ void intel_ddi_init(struct intel_display *display, encoder->enable_clock = intel_xe3plpd_pll_enable; encoder->disable_clock = intel_xe3plpd_pll_disable; encoder->port_pll_type = intel_mtl_port_pll_type; + encoder->get_config = xe3plpd_ddi_get_config; } else if (DISPLAY_VER(display) >= 14) { encoder->enable_clock = intel_mtl_pll_enable; encoder->disable_clock = intel_mtl_pll_disable; |