diff options
| author | Karthi Kandasamy <karthi.kandasamy@amd.com> | 2026-05-28 12:49:44 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-08-06 09:58:41 -0400 |
| commit | 73efd24e21e630b497b3447bc8d2eb550bf9e1fa (patch) | |
| tree | cea97fdeb74f3cff54cbd06ea4176231c7680fb1 /drivers/gpu/drm/amd/display/modules | |
| parent | 8b87300e1b2a747a608c5036ea57bb9dcd91d82b (diff) | |
| download | linux-next-73efd24e21e630b497b3447bc8d2eb550bf9e1fa.tar.gz linux-next-73efd24e21e630b497b3447bc8d2eb550bf9e1fa.zip | |
drm/amd/display: Fix seamless mode switch not triggering for HDR to SDR transition
[Why]
The seamless mode switch was not getting triggered during HDR to SDR
transitions, and no DPCD write was observed. Root cause analysis
revealed that incorrect panel capabilities were being reported for PSR
SU panels. Due to the wrong capabilities, the OS was not invoking the
seamless mode switch API, resulting in no DPCD communication and also
gated eDP teardown across the seamless mode switch hold.
[How]
Fixed by setting the correct power panel capabilities for PSR SU panels.
This ensures the OS receives accurate panel capability information and
triggers the seamless mode switch API as expected, restoring proper
DPCD writes during HDR to SDR transitions.
The DC commit sequence was tearing the eDP down anyway -- backlight off,
ABM disable, DPMS off, PSR/Replay enable state cleared, PHY TX off,
OTG/OPTC off; all these actions are blocked now with the
skip_implict_edp_power_control
Reviewed-by: Aric Cyr <aric.cyr@amd.com>
Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules')
| -rw-r--r-- | drivers/gpu/drm/amd/display/modules/power/power_psr.c | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/modules/power/power_replay.c | 7 |
2 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_psr.c b/drivers/gpu/drm/amd/display/modules/power/power_psr.c index 5ecb570c204e..96bb77fff05b 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_psr.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_psr.c @@ -58,6 +58,13 @@ bool mod_power_psr_notify_mode_change(struct mod_power *mod_power, // stream_index is passed as validated parameter active_psr_events = core_power->map[stream_index].psr_events; + /* forced psr is active for seamless switch. + * Re-running edp_setup_psr would disturb the freeze, + * so skip the PSR re-setup until forced psr releases the override. + */ + if (active_psr_events & psr_event_os_override_hold) + return false; + /* Calculate PSR configurations */ mod_power_calc_psr_configs(&psr_config, link, stream); diff --git a/drivers/gpu/drm/amd/display/modules/power/power_replay.c b/drivers/gpu/drm/amd/display/modules/power/power_replay.c index e782501442c4..31d9cb3a12ba 100644 --- a/drivers/gpu/drm/amd/display/modules/power/power_replay.c +++ b/drivers/gpu/drm/amd/display/modules/power/power_replay.c @@ -805,6 +805,13 @@ void mod_power_replay_notify_mode_change(struct mod_power *mod_power, core_power = MOD_POWER_TO_CORE(mod_power); active_replay_events = core_power->map[stream_index].replay_events; + /* forced psr is active for seamless switch. + * Re-running edp_setup_psr would disturb the freeze, + * so skip the PSR re-setup until forced psr releases the override. + */ + if (active_replay_events & replay_event_os_override_hold) + return; + link->replay_settings.replay_smu_opt_enable = (link->replay_settings.config.replay_smu_opt_supported && mod_power_only_edp(dc->current_state, stream)); |
