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authorKarthi Kandasamy <karthi.kandasamy@amd.com>2026-05-28 12:49:44 +0200
committerAlex Deucher <alexander.deucher@amd.com>2026-07-15 09:15:40 -0400
commit1f07e9fddc4a29a71a935fc20b7f894767327314 (patch)
tree85b9ca07168858ee130fc3350073e5cfcd4df41f /drivers/gpu/drm/amd/display/modules/power
parent66251e0d45dafe5c119d79523c07d849a9444dc7 (diff)
downloadlinux-next-1f07e9fddc4a29a71a935fc20b7f894767327314.tar.gz
linux-next-1f07e9fddc4a29a71a935fc20b7f894767327314.zip
drm/amd/display: Fix DMSS not triggering for HDR to SDR transition
Why: DMSS feature was not getting triggered during HDR to SDR transitions, and no DPCD write was observed. Root cause analysis revealed that incorrect panel capabilities were being reported for PSR SU panels. Due to the wrong capabilities, the OS was not invoking the DMSS API, resulting in no DPCD communication and also gate eDP teardown across DMSS hold How: Fixed by setting the correct power panel capabilities for PSR SU panels. This ensures the OS receives accurate panel capability information and triggers the DMSS API as expected, restoring proper DPCD writes during HDR to SDR transitions. The DC commit sequence,was tearing the eDP down anyway -- backlight off, ABM disable, DPMS off, PSR/Replay feature_enabled cleared, PHY TX off, OTG/OPTC off all these actions are blocked now with the skip_implict_edp_power_control Reviewed-by: Aric Cyr <aric.cyr@amd.com> Signed-off-by: Karthi Kandasamy <karthi.kandasamy@amd.com> Signed-off-by: George Zhang <george.zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/modules/power')
-rw-r--r--drivers/gpu/drm/amd/display/modules/power/power_psr.c7
-rw-r--r--drivers/gpu/drm/amd/display/modules/power/power_replay.c7
2 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_psr.c b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
index 5ecb570c204e..0ad4c4924696 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_psr.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_psr.c
@@ -58,6 +58,13 @@ bool mod_power_psr_notify_mode_change(struct mod_power *mod_power,
// stream_index is passed as validated parameter
active_psr_events = core_power->map[stream_index].psr_events;
+ /* DMSS holds the panel in a forced PSR freeze (e.g. during HDR/SDR toggle).
+ * Re-running edp_setup_psr would reprogram DPCD 0x170 and disturb the freeze,
+ * so skip the PSR re-setup until DMSS releases the override.
+ */
+ if (active_psr_events & psr_event_os_override_hold)
+ return false;
+
/* Calculate PSR configurations */
mod_power_calc_psr_configs(&psr_config, link, stream);
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_replay.c b/drivers/gpu/drm/amd/display/modules/power/power_replay.c
index e782501442c4..1ad2ee01d560 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_replay.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_replay.c
@@ -805,6 +805,13 @@ void mod_power_replay_notify_mode_change(struct mod_power *mod_power,
core_power = MOD_POWER_TO_CORE(mod_power);
active_replay_events = core_power->map[stream_index].replay_events;
+ /* DMSS holds the panel in a forced freeze (e.g. during HDR/SDR toggle).
+ * Re-running dp_setup_replay would reprogram DPCD 0x37B and disturb the
+ * freeze, so skip the replay re-setup until DMSS releases the override.
+ */
+ if (active_replay_events & replay_event_os_override_hold)
+ return;
+
link->replay_settings.replay_smu_opt_enable =
(link->replay_settings.config.replay_smu_opt_supported &&
mod_power_only_edp(dc->current_state, stream));