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| author | Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> | 2026-07-23 14:19:41 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-08-25 18:25:24 -0400 |
| commit | cadc58e024fa78c9f62f3940eb53295ddf6c5b24 (patch) | |
| tree | 1b6a6f5fadec64acbb73058530d8a942154a4d4b /drivers/gpu/drm/amd/display/include | |
| parent | 50eed169c0ab2a433a2ff9e95a3cc45ebb4dafaa (diff) | |
| download | linux-next-cadc58e024fa78c9f62f3940eb53295ddf6c5b24.tar.gz linux-next-cadc58e024fa78c9f62f3940eb53295ddf6c5b24.zip | |
drm/amd/display: Fix HostVM init and SOCBB VM config for DCN6
[Why]
Underflow occurs in testing for DCHVM and RIOMMU interop tests when
attempting to scan out surfaces in VM.
[How]
New registers have been added to DCN6 for HostVM to control which VFID
to prefetch by default. These need to be programmed during the VM init
sequence. The sequence validated from DCN42 is used (and xref'd with
the design documentation with hardware) with the register placed in
an ordering that appears correct.
HostVM and GPUVM are also currently disabled and set an incorrect
number of page table levels and min page size in the SOCBB for DCN6b.
These are updated, but driver also needs to select the B variant when
creating the SOC BB to ensure that they're piped into DML.
Lastly, the init function for the vm context is branched out to skip
initializing VMID 15 - this workaround should no longer be necessary
on DCN6.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/include')
| -rw-r--r-- | drivers/gpu/drm/amd/display/include/dal_asic_id.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 7ed785be8473..f4c6ddb6378e 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -275,6 +275,8 @@ enum { DCN6_VARIANT2_B0 = 0x11, DCN6_VARIANT3_A0 = 0x20, DCN6_VARIANT3_UPPER = 0x2F, + DCN6_VARIANT_LITE3_A0 = 0x50, + DCN6_VARIANT_LITE3_B0 = 0x51, DCN6_UNKNOWN = 0xFF }; @@ -284,6 +286,9 @@ enum { #define ASICREV_IS_DCN6_VARIANT2_A0(eChipRev) (eChipRev >= DCN6_VARIANT2_A0 && eChipRev < DCN6_VARIANT2_B0) #define ASICREV_IS_DCN6_VARIANT2_B0(eChipRev) (eChipRev >= DCN6_VARIANT2_B0 && eChipRev < DCN6_VARIANT3_A0) #define ASICREV_IS_DCN6_VARIANT3(eChipRev) (eChipRev >= DCN6_VARIANT3_A0 && eChipRev <= DCN6_VARIANT3_UPPER) +#define ASICREV_IS_DCN6_VARIANT_LITE3(eChipRev) (eChipRev >= DCN6_VARIANT_LITE3_A0 && eChipRev < DCN6_UNKNOWN) +#define ASICREV_IS_DCN6_VARIANT_LITE3_A0(eChipRev) (eChipRev >= DCN6_VARIANT_LITE3_A0 && eChipRev < DCN6_VARIANT_LITE3_B0) +#define ASICREV_IS_DCN6_VARIANT_LITE3_B0(eChipRev) (eChipRev >= DCN6_VARIANT_LITE3_B0 && eChipRev < DCN6_UNKNOWN) enum { GC_12_0_0_A0 = 0x50, |