diff options
| author | Ovidiu Bunea <ovidiu.bunea@amd.com> | 2026-07-30 23:50:04 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-08-25 18:25:27 -0400 |
| commit | 7dd3e8cc110fe954bcdd988069fee8eee758c66a (patch) | |
| tree | 85c9121fc0c318b960791148b8f9f84b72f24867 /drivers/gpu/drm/amd/display/dmub | |
| parent | 322a0695ac2ccbef507ec9b1534885c90bf8259b (diff) | |
| download | linux-next-7dd3e8cc110fe954bcdd988069fee8eee758c66a.tar.gz linux-next-7dd3e8cc110fe954bcdd988069fee8eee758c66a.zip | |
drm/amd/display: Send DPM0 clock values to DMU
[why & how]
Z8 Retention requires clocks to be put into bypass for the PLL
to be powered down.
Notify DMU of the DPM0 clock values, which is likely always going
to be running of a bypass clock.
Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com>
Signed-off-by: James Lin <pinglei.lin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index c273d97ec88d..1d10fe8f1998 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -3009,6 +3009,9 @@ struct dmub_clocks { uint32_t dppclk_khz; /**< dppclk kHz */ uint32_t dcfclk_khz; /**< dcfclk kHz */ uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */ + uint32_t dpm0_dispclk_khz; /**< DPM0 (minimum) dispclk kHz from SMU DPM table, 0 if unknown */ + uint32_t dpm0_dppclk_khz; /**< DPM0 (minimum) dppclk kHz from SMU DPM table, 0 if unknown */ + uint32_t max_bypass_clk_khz; /**< max dispclk/dppclk achievable on a bypass source (no PLL) kHz, 0 if unknown */ }; /** |