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| author | Harry Wentland <harry.wentland@amd.com> | 2026-04-24 14:23:45 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-06-03 13:44:46 -0400 |
| commit | fdaf63d9a83aeff2f165b45e7073767bbe62f2fc (patch) | |
| tree | 14b0b8ae117ed34ba71d9d91474480dd48641287 /drivers/gpu/drm/amd/display/dmub/inc | |
| parent | cbb8e2044b9e936dfa66f1d4a2f835316c741a67 (diff) | |
| download | linux-next-fdaf63d9a83aeff2f165b45e7073767bbe62f2fc.tar.gz linux-next-fdaf63d9a83aeff2f165b45e7073767bbe62f2fc.zip | |
drm/amd/display: Add support for FRL to DC core
Here we add support for reading BIOS caps and tie FRL bits
into the rest of DC core.
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 6f0c4b602f89..6f6a59a23495 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -2985,16 +2985,19 @@ struct dmub_dig_transmitter_control_data_v1_7 { union { uint8_t digmode; /**< enum atom_encode_mode_def */ uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */ + uint8_t txffe; /**< TxFFE settings for HDMI 2.1 */ } mode_laneset; uint8_t lanenum; /**< Number of lanes */ union { uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */ + uint32_t symclk_Hz; /**< Symbol clock in Hz for FRL */ } symclk_units; uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */ uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */ uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */ uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */ - uint8_t reserved1; /**< For future use */ + uint8_t TxFFELaneSel; /**< TxFFE lane select [3:0] + (bit0: lane0, bit1: lane1, bit2: lane3, bit3: lane3) */ uint8_t skip_phy_ssc_reduction; uint8_t reserved2[2]; /**< For future use */ uint32_t reserved3[11]; /**< For future use */ |