diff options
| author | Nicholas Carbones <ncarbone@amd.com> | 2026-01-06 17:35:51 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-02-03 16:40:10 -0500 |
| commit | 08a01ec306dbd0e096be8ee0cebb0e6a3b5fa413 (patch) | |
| tree | ea7286a86faaf3effaa974a0cba790da842ff17e /drivers/gpu/drm/amd/display/dc/dce | |
| parent | 9d6bd60695806782bec8562ab73aefafce067f05 (diff) | |
| download | linux-next-08a01ec306dbd0e096be8ee0cebb0e6a3b5fa413.tar.gz linux-next-08a01ec306dbd0e096be8ee0cebb0e6a3b5fa413.zip | |
drm/amd/display: Add Gfx Base Case For Linear Tiling Handling
[Why]
Post-driver cases always use linear tiling yet there is no dedicated
Gfx handling for this condition.
[How]
Add DcGfxBase/DalGfxBase to gfx version enums and set tiling to linear
when it is used. Also, enforce the use of proper tiling format as tiling
information is used.
Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Nicholas Carbones <ncarbone@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c index 1c2009e38aa1..5df58fadc862 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c @@ -100,6 +100,7 @@ static enum mi_bits_per_pixel get_mi_bpp( static enum mi_tiling_format get_mi_tiling( struct dc_tiling_info *tiling_info) { + ASSERT(tiling_info->gfxversion == DcGfxVersion8); switch (tiling_info->gfx8.array_mode) { case DC_ARRAY_1D_TILED_THIN1: case DC_ARRAY_1D_TILED_THICK: @@ -433,6 +434,7 @@ static void program_tiling( struct dce_mem_input *dce_mi, const struct dc_tiling_info *info) { if (dce_mi->masks->GRPH_SW_MODE) { /* GFX9 */ + ASSERT(info->gfxversion == DcGfxVersion9); REG_UPDATE_6(GRPH_CONTROL, GRPH_SW_MODE, info->gfx9.swizzle, GRPH_NUM_BANKS, log_2(info->gfx9.num_banks), @@ -447,6 +449,7 @@ static void program_tiling( } if (dce_mi->masks->GRPH_MICRO_TILE_MODE) { /* GFX8 */ + ASSERT(info->gfxversion == DcGfxVersion8); REG_UPDATE_9(GRPH_CONTROL, GRPH_NUM_BANKS, info->gfx8.num_banks, GRPH_BANK_WIDTH, info->gfx8.bank_width, |