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authorAlex Deucher <alexander.deucher@amd.com>2026-08-14 11:39:16 -0400
committerAlex Deucher <alexander.deucher@amd.com>2026-08-19 10:13:33 -0400
commit0e4ef0ead600e367b4dd431daa97a345a5ff8a86 (patch)
treefa2e8b04dab9e710cc25784cfdfe5be17983fbcd /drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
parent4d7390530853eb7befda9cc786e4c86e8ad7ac9e (diff)
downloadlinux-next-0e4ef0ead600e367b4dd431daa97a345a5ff8a86.tar.gz
linux-next-0e4ef0ead600e367b4dd431daa97a345a5ff8a86.zip
drm/amdgpu: handle pipeline sync without a VM fence
If we end up emitting a VM fence keep pipeline sync associated with that fence. If not, emit them as part of the IB fence. v2: fix need_pipe_sync handling v3: simplify the function Cc: David Rosca <david.rosca@amd.com> Fixes: cb1e657ccac8 ("drm/amdgpu: handle GDS and SPM without a VM fence") Reviewed-by: David Rosca <david.rosca@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index da4dc489e80b..360e6f00cb7c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -222,7 +222,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
vm_af = job->hw_vm_fence;
/* VM sequence */
vm_af->ib_wptr = ring->wptr;
- amdgpu_vm_flush(ring, job, need_pipe_sync, &emit_spm_needed,
+ amdgpu_vm_flush(ring, job, &need_pipe_sync, &emit_spm_needed,
&emit_gds_needed);
vm_af->ib_dw_size =
amdgpu_ring_get_dw_distance(ring, vm_af->ib_wptr, ring->wptr);
@@ -235,6 +235,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs,
if (ring->funcs->insert_start)
ring->funcs->insert_start(ring);
+ /* this may have been handled by amdgpu_vm_flush */
+ if (need_pipe_sync)
+ amdgpu_ring_emit_pipeline_sync(ring);
+
if (emit_spm_needed)
adev->gfx.rlc.funcs->update_spm_vmid(adev, ring->xcc_id, ring, job->vmid);