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| author | Timur Kristóf <timur.kristof@gmail.com> | 2026-06-17 21:14:22 +0200 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-07-01 11:14:11 -0400 |
| commit | 1fc76380c6ce5440e3cd02ddec76067f83969dc0 (patch) | |
| tree | ba77e56366b5eb9f6df4f0454903e8eef9e0bb48 /drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | |
| parent | b7500532e12b32d9ac54a4faacebb12baca091a4 (diff) | |
| download | linux-next-1fc76380c6ce5440e3cd02ddec76067f83969dc0.tar.gz linux-next-1fc76380c6ce5440e3cd02ddec76067f83969dc0.zip | |
drm/amdgpu: Add IP block soft reset as a GPU recovery method
Implement IP block soft reset as a recovery method that fits into
the current GPU recovery code as opposed to being hacked into the
full GPU reset code path.
This can gracefully handle GPU hangs when other reset methods
are not available or have failed. It makes sure to minimize
collateral damage (ie. affected non-guilty jobs) and does a
backup and restore on all affected queues.
Note that some of the new helpers may be useful for other
reset types as well, which we can explore later.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 157c0f260cc0..f5e8e4f455ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -147,6 +147,7 @@ enum AMDGPU_DEBUG_MASK { AMDGPU_DEBUG_DISABLE_RAS_CE_LOG = BIT(9), AMDGPU_DEBUG_ENABLE_CE_CS = BIT(10), AMDGPU_DEBUG_HIBERNATION_THAW_RESUME_GPU = BIT(11), + AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET = BIT(12), }; unsigned int amdgpu_vram_limit = UINT_MAX; @@ -2296,6 +2297,11 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev) pr_info("debug: resume gpu in thaw() of hibernation\n"); adev->debug_hibernation_thaw_resume_gpu = true; } + + if (amdgpu_debug_mask & AMDGPU_DEBUG_DISABLE_IP_BLOCK_SOFT_RESET) { + pr_info("debug: IP block soft reset disabled\n"); + adev->debug_disable_ip_block_soft_reset = true; + } } static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) |