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| author | Maxime Ripard <mripard@kernel.org> | 2026-02-23 10:09:45 +0100 |
|---|---|---|
| committer | Maxime Ripard <mripard@kernel.org> | 2026-02-23 10:09:45 +0100 |
| commit | c17ee635fd3a482b2ad2bf5e269755c2eae5f25e (patch) | |
| tree | e3f147462d8a9fd0cf2312c8cd3c5a94da15c3e4 /drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | |
| parent | 803ec1faf7c1823e6e3b1f2aaa81be18528c9436 (diff) | |
| parent | 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f (diff) | |
| download | linux-next-c17ee635fd3a482b2ad2bf5e269755c2eae5f25e.tar.gz linux-next-c17ee635fd3a482b2ad2bf5e269755c2eae5f25e.zip | |
Merge drm/drm-fixes into drm-misc-fixes
7.0-rc1 was just released, let's merge it to kick the new release cycle.
Signed-off-by: Maxime Ripard <mripard@kernel.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h index 2675689ef70f..ebd14c292978 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_doorbell.h @@ -348,6 +348,36 @@ enum AMDGPU_DOORBELL_ASSIGNMENT_LAYOUT1 { AMDGPU_DOORBELL_LAYOUT1_INVALID = 0xFFFF }; +enum AMDGPU_SOC_V1_0_DOORBELL_ASSIGNMENT { + /* KIQ/HIQ/DIQ */ + AMDGPU_SOC_V1_0_DOORBELL_KIQ_START = 0x000, + AMDGPU_SOC_V1_0_DOORBELL_HIQ = 0x001, + AMDGPU_SOC_V1_0_DOORBELL_DIQ = 0x002, + /* Compute: 0x03 ~ 0x20 */ + AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_START = 0x003, + AMDGPU_SOC_V1_0_DOORBELL_MEC_RING_END = 0x00A, + AMDGPU_SOC_V1_0_DOORBELL_MES_RING0 = 0x00B, + AMDGPU_SOC_V1_0_DOORBELL_MES_RING1 = 0x00C, + AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_START = 0x00D, + AMDGPU_SOC_V1_0_DOORBELL_USERQUEUE_END = 0x01F, + AMDGPU_SOC_V1_0_DOORBELL_XCC_RANGE = 0x020, + + /* SDMA: 0x100 ~ 0x19F */ + AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START = 0x100, + AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_END = 0x19F, + /* IH: 0x1A0 ~ 0x1AF */ + AMDGPU_SOC_V1_0_DOORBELL_IH = 0x1A0, + /* VCN: 0x1B0 ~ 0x1EF */ + AMDGPU_SOC_V1_0_DOORBELL_VCN_START = 0x1B0, + AMDGPU_SOC_V1_0_DOORBELL_VCN_END = 0x1EF, + + AMDGPU_SOC_V1_0_DOORBELL_FIRST_NON_CP = AMDGPU_SOC_V1_0_DOORBELL_sDMA_ENGINE_START, + AMDGPU_SOC_V1_0_DOORBELL_LAST_NON_CP = AMDGPU_SOC_V1_0_DOORBELL_VCN_END, + + AMDGPU_SOC_V1_0_DOORBELL_MAX_ASSIGNMENT = 0x1EF, + AMDGPU_SOC_V1_0_DOORBELL_INVALID = 0xFFFF +}; + u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index); |