diff options
| author | Abel Vesa <abel.vesa@oss.qualcomm.com> | 2026-09-24 15:06:18 +0300 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2026-09-25 11:27:12 -0500 |
| commit | 7455a58f12d121e9a6f7077974bc1d693e171421 (patch) | |
| tree | d86c798d34fa563e2925e424962db6a1630b3d92 /drivers/clk | |
| parent | d8d527f0c0d99cce7d6746e2ea5bec628a2aab4b (diff) | |
| download | linux-next-7455a58f12d121e9a6f7077974bc1d693e171421.tar.gz linux-next-7455a58f12d121e9a6f7077974bc1d693e171421.zip | |
clk: qcom: dispcc-sc8280xp: Use common probe handling for always-on clocks
Describe the always-on branches in a critical_cbcrs array and reference
it through qcom_cc_driver_data. Let qcom_cc_really_probe() enable these
branches instead of programming them directly in the driver's probe.
Share the CBCR data between the two display controller descriptors. The
XO branch is now enabled by the common probe before clock registration.
Assisted-by: LLM
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20260924-clk-qcom-rework-legacy-always-on-clocks-v2-6-1479443ee016@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/qcom/dispcc-sc8280xp.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/drivers/clk/qcom/dispcc-sc8280xp.c b/drivers/clk/qcom/dispcc-sc8280xp.c index 96609bd5233f..96b3e5505279 100644 --- a/drivers/clk/qcom/dispcc-sc8280xp.c +++ b/drivers/clk/qcom/dispcc-sc8280xp.c @@ -3108,7 +3108,17 @@ static const struct regmap_config disp_cc_sc8280xp_regmap_config = { .fast_io = true, }; +static const u32 disp_cc_sc8280xp_critical_cbcrs[] = { + 0x605c, /* DISP_CC_XO_CLK */ +}; + +static const struct qcom_cc_driver_data disp_cc_sc8280xp_driver_data = { + .clk_cbcrs = disp_cc_sc8280xp_critical_cbcrs, + .num_clk_cbcrs = ARRAY_SIZE(disp_cc_sc8280xp_critical_cbcrs), +}; + static const struct qcom_cc_desc disp0_cc_sc8280xp_desc = { + .driver_data = &disp_cc_sc8280xp_driver_data, .config = &disp_cc_sc8280xp_regmap_config, .clks = disp0_cc_sc8280xp_clocks, .num_clks = ARRAY_SIZE(disp0_cc_sc8280xp_clocks), @@ -3119,6 +3129,7 @@ static const struct qcom_cc_desc disp0_cc_sc8280xp_desc = { }; static const struct qcom_cc_desc disp1_cc_sc8280xp_desc = { + .driver_data = &disp_cc_sc8280xp_driver_data, .config = &disp_cc_sc8280xp_regmap_config, .clks = disp1_cc_sc8280xp_clocks, .num_clks = ARRAY_SIZE(disp1_cc_sc8280xp_clocks), @@ -3167,13 +3178,8 @@ static int disp_cc_sc8280xp_probe(struct platform_device *pdev) clk_lucid_pll_configure(clkr_to_alpha_clk_pll(desc->clks[DISP_CC_PLL2]), regmap, &disp_cc_pll2_config); ret = qcom_cc_really_probe(&pdev->dev, desc, regmap); - if (ret) { + if (ret) dev_err(&pdev->dev, "Failed to register display clock controller\n"); - goto out_pm_runtime_put; - } - - /* Keep some clocks always-on */ - qcom_branch_set_clk_en(regmap, 0x605c); /* DISP_CC_XO_CLK */ out_pm_runtime_put: pm_runtime_put_sync(&pdev->dev); |