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| author | Juergen Gross <jgross@suse.com> | 2026-07-03 12:55:55 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2026-07-19 11:39:18 +0200 |
| commit | a7187ca1e72505fd6785b0ce537ae066773a5532 (patch) | |
| tree | f2cb992ce696f22c1019f2416d2976200d16457d /arch/x86/kernel | |
| parent | e8caa0abfbf0283874582e8160cef5fca845ffb8 (diff) | |
| download | linux-next-a7187ca1e72505fd6785b0ce537ae066773a5532.tar.gz linux-next-a7187ca1e72505fd6785b0ce537ae066773a5532.zip | |
x86/mce: Work around build warning after MSR-interface switch
The recent switch to 64-bit MSR interfaces introduced a build warning.
Work it around with a __maybe_unused annotation. After the full conversion
of the APIs we'll be able to address this more robustly by making sure
the APIs consume all the values as far the compiler is concerned, so that
the compiler doesn't emit such nuisance warnings.
[ mingo: Updated the changelog. ]
Fixes: cff219368bd0 ("x86/mce: Stop using 32-bit MSR interfaces")
Closes: https://lore.kernel.org/oe-kbuild-all/202607031726.ZOwu4snu-lkp@intel.com/
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://patch.msgid.link/20260703105555.1758819-1-jgross@suse.com
Diffstat (limited to 'arch/x86/kernel')
| -rw-r--r-- | arch/x86/kernel/cpu/mce/p5.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/mce/p5.c b/arch/x86/kernel/cpu/mce/p5.c index eb99f384d747..3c2b6cc918b1 100644 --- a/arch/x86/kernel/cpu/mce/p5.c +++ b/arch/x86/kernel/cpu/mce/p5.c @@ -44,7 +44,7 @@ noinstr void pentium_machine_check(struct pt_regs *regs) /* Set up machine check reporting for processors with Intel style MCE: */ void intel_p5_mcheck_init(struct cpuinfo_x86 *c) { - u64 q; + u64 __maybe_unused q; /* Default P5 to off as its often misconnected: */ if (!mce_p5_enabled) |