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| author | Ingo Molnar <mingo@kernel.org> | 2026-07-08 10:28:05 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2026-07-08 10:28:05 +0200 |
| commit | c364506b98ef947174c1e8554c6861383712e141 (patch) | |
| tree | 1c3d5d03f9f216427e78cd7843931dae14697255 /arch/x86/kernel/process.c | |
| parent | ea4cd413acda6e64b64cd55afc5f14670d4f8a07 (diff) | |
| parent | 3eaa50e1e255ec261c757b9eea811ef3bac10d1e (diff) | |
| download | linux-next-c364506b98ef947174c1e8554c6861383712e141.tar.gz linux-next-c364506b98ef947174c1e8554c6861383712e141.zip | |
Merge branch 'x86/cpu' into perf/merge, to resolve conflict
Conflicts:
arch/x86/events/intel/lbr.c
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Diffstat (limited to 'arch/x86/kernel/process.c')
| -rw-r--r-- | arch/x86/kernel/process.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index 85435044e33c..346c438ac880 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c @@ -579,7 +579,7 @@ static __always_inline void amd_set_core_ssb_state(unsigned long tifn) struct ssb_state *st = this_cpu_ptr(&ssb_state); u64 msr = x86_amd_ls_cfg_base; - if (!static_cpu_has(X86_FEATURE_ZEN)) { + if (!cpu_feature_enabled(X86_FEATURE_ZEN)) { msr |= ssbd_tif_to_amd_ls_cfg(tifn); wrmsrq(MSR_AMD64_LS_CFG, msr); return; @@ -646,14 +646,14 @@ static __always_inline void __speculation_ctrl_update(unsigned long tifp, lockdep_assert_irqs_disabled(); /* Handle change of TIF_SSBD depending on the mitigation method. */ - if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) { + if (cpu_feature_enabled(X86_FEATURE_VIRT_SSBD)) { if (tif_diff & _TIF_SSBD) amd_set_ssb_virt_state(tifn); - } else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) { + } else if (cpu_feature_enabled(X86_FEATURE_LS_CFG_SSBD)) { if (tif_diff & _TIF_SSBD) amd_set_core_ssb_state(tifn); - } else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) || - static_cpu_has(X86_FEATURE_AMD_SSBD)) { + } else if (cpu_feature_enabled(X86_FEATURE_SPEC_CTRL_SSBD) || + cpu_feature_enabled(X86_FEATURE_AMD_SSBD)) { updmsr |= !!(tif_diff & _TIF_SSBD); msr |= ssbd_tif_to_spec_ctrl(tifn); } |