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authorPeter Zijlstra <peterz@infradead.org>2026-05-19 12:18:01 +0200
committerPeter Zijlstra <peterz@infradead.org>2026-05-19 12:18:01 +0200
commita26d9208c1376ac3877d9f12e697f83368e2af1c (patch)
tree1f68b9ae26b8b88a7d1f24fea2a6df87e4c0fee5 /arch/x86/include
parentdd29c017aed628076e915fe4cdfb5392fd4c5cab (diff)
parentc99b8593b060931c5a0a4b701689f8d6a2c00dbf (diff)
downloadlinux-next-a26d9208c1376ac3877d9f12e697f83368e2af1c.tar.gz
linux-next-a26d9208c1376ac3877d9f12e697f83368e2af1c.zip
Merge branch 'sched/cache'
Merge the cache aware balancer topic branch. # Conflicts: # kernel/sched/topology.c
Diffstat (limited to 'arch/x86/include')
-rw-r--r--arch/x86/include/asm/processor.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 10b5355b323e..eb9fce94620d 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -704,6 +704,11 @@ static inline u32 per_cpu_l2c_id(unsigned int cpu)
return per_cpu(cpu_info.topo.l2c_id, cpu);
}
+static inline u32 per_cpu_core_id(unsigned int cpu)
+{
+ return per_cpu(cpu_info.topo.core_id, cpu);
+}
+
#ifdef CONFIG_CPU_SUP_AMD
/*
* Issue a DIV 0/1 insn to clear any division data from previous DIV