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| author | Marc Zyngier <maz@kernel.org> | 2025-11-20 17:24:56 +0000 |
|---|---|---|
| committer | Oliver Upton <oupton@kernel.org> | 2025-11-24 14:29:11 -0800 |
| commit | 2a28810cbb8b21a4016182617cc1fd72eddf4a36 (patch) | |
| tree | fbe99281eac800a46aacb8056aa766117eb65053 /arch/arm64/tools | |
| parent | 567ebfedb5bd204a8ce6a11695f02730f1bf57f4 (diff) | |
| download | linux-next-2a28810cbb8b21a4016182617cc1fd72eddf4a36.tar.gz linux-next-2a28810cbb8b21a4016182617cc1fd72eddf4a36.zip | |
KVM: arm64: GICv3: Detect and work around the lack of ICV_DIR_EL1 trapping
A long time ago, an unsuspecting architect forgot to add a trap
bit for ICV_DIR_EL1 in ICH_HCR_EL2. Which was unfortunate, but
what's a bit of spec between friends? Thankfully, this was fixed
in a later revision, and ARM "deprecates" the lack of trapping
ability.
Unfortuantely, a few (billion) CPUs went out with that defect,
anything ARMv8.0 from ARM, give or take. And on these CPUs,
you can't trap DIR on its own, full stop.
As the next best thing, we can trap everything in the common group,
which is a tad expensive, but hey ho, that's what you get. You can
otherwise recycle the HW in the neaby bin.
Tested-by: Fuad Tabba <tabba@google.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Tested-by: Mark Brown <broonie@kernel.org>
Link: https://msgid.link/20251120172540.2267180-7-maz@kernel.org
Signed-off-by: Oliver Upton <oupton@kernel.org>
Diffstat (limited to 'arch/arm64/tools')
| -rw-r--r-- | arch/arm64/tools/cpucaps | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps index 1b32c1232d28..116d1a7b688c 100644 --- a/arch/arm64/tools/cpucaps +++ b/arch/arm64/tools/cpucaps @@ -40,6 +40,7 @@ HAS_GICV5_CPUIF HAS_GICV5_LEGACY HAS_GIC_PRIO_MASKING HAS_GIC_PRIO_RELAXED_SYNC +HAS_ICH_HCR_EL2_TDIR HAS_HCR_NV1 HAS_HCX HAS_LDAPR |