diff options
| author | Eberhard Stoll <eberhard.stoll@kontron.de> | 2026-09-14 15:46:09 +0200 |
|---|---|---|
| committer | Frank Li <Frank.Li@nxp.com> | 2026-09-23 16:21:16 -0400 |
| commit | b2e2c41c398d6aa097203e70c7acf82ba4c5a6a0 (patch) | |
| tree | 5b1e6adcdb224d50e583b88d86490bfc29f86493 /arch/arm/boot | |
| parent | 1fa2b2c7b7b8563161412be16880651e197d2bb6 (diff) | |
| download | linux-next-b2e2c41c398d6aa097203e70c7acf82ba4c5a6a0.tar.gz linux-next-b2e2c41c398d6aa097203e70c7acf82ba4c5a6a0.zip | |
ARM: dts: imx6ul-kontron-bl-common: Replace UART3 with DIP switch GPIOs
The latest board revision has DIP switches and lacks UART3 instead.
As the old revision has long been deprecated and not maintained
anymore, drop the support and reflect the current state of the
hardware. As the old revision hasn't been widely used and UART3 was
only available through an obscure extension connector, no users are
expected to be affected by this change.
Signed-off-by: Eberhard Stoll <eberhard.stoll@kontron.de>
Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Diffstat (limited to 'arch/arm/boot')
| -rw-r--r-- | arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi | 21 |
1 files changed, 5 insertions, 16 deletions
diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi index f4c45e964daf..a71669bef7d4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-kontron-bl-common.dtsi @@ -172,13 +172,6 @@ status = "okay"; }; -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -283,6 +276,11 @@ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */ + + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x1b0b0 /* CAN_ADR0 (DIP sw 1) */ + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* CAN_ADR1 (DIP sw 2) */ + MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* CAN_ADR2 (DIP sw 3) */ + MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x1b0b0 /* CAN_ADR3 (DIP sw 4) */ >; }; @@ -334,15 +332,6 @@ >; }; - pinctrl_uart3: uart3grp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1 - MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1 - MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1 - >; - }; - pinctrl_uart4: uart4grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1 |