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| author | Mark Brown <broonie@kernel.org> | 2026-07-26 23:42:04 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-07-26 23:42:04 +0100 |
| commit | 6998538ebe42a24094359b820b535695fdf3660a (patch) | |
| tree | 537d55fba721818e26e44f33b562df489874010b /Documentation/devicetree | |
| parent | 4cc13adbc59e8fc4d52e9d2808f12c53dbb22ffd (diff) | |
| parent | 0613e7934ee233d726af8d8c89f251a1c4df738d (diff) | |
| download | linux-next-6998538ebe42a24094359b820b535695fdf3660a.tar.gz linux-next-6998538ebe42a24094359b820b535695fdf3660a.zip | |
Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git
Diffstat (limited to 'Documentation/devicetree')
4 files changed, 12 insertions, 6 deletions
diff --git a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml index 391bf5838602..bea302b89453 100644 --- a/Documentation/devicetree/bindings/dma/altr,msgdma.yaml +++ b/Documentation/devicetree/bindings/dma/altr,msgdma.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera mSGDMA IP core maintainers: - - Olivier Dautricourt <olivierdautricourt@gmail.com> + - Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> description: | Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA) diff --git a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml index 3708518fe7fc..bba20e88a6dc 100644 --- a/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml +++ b/Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml @@ -40,6 +40,7 @@ properties: - items: - enum: - mediatek,mt6991-uart-dma + - mediatek,mt8189-uart-dma - mediatek,mt8196-uart-dma - const: mediatek,mt6985-uart-dma - enum: diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 0923fb189ada..e72adc172af1 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -48,7 +48,7 @@ properties: iommus: minItems: 1 - maxItems: 6 + maxItems: 7 num-channels: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml index 340ae9e91cb0..2c88e927d9d3 100644 --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml @@ -81,8 +81,13 @@ properties: description: Should be the number of framebuffers as configured in h/w. xlnx,flush-fsync: - type: boolean - description: Tells which channel to Flush on Frame sync. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: + Tells which channel to flush on frame sync. + 1 - flush both channels + 2 - flush mm2s channel + 3 - flush s2mm channel xlnx,sg-length-width: $ref: /schemas/types.yaml#/definitions/uint32 @@ -93,7 +98,7 @@ properties: Width in bits of the length register as configured in hardware. xlnx,irq-delay: - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint8 minimum: 0 maximum: 255 description: @@ -251,7 +256,7 @@ examples: "m_axi_s2mm_aclk", "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; xlnx,num-fstores = <8>; - xlnx,flush-fsync; + xlnx,flush-fsync = <1>; xlnx,addrwidth = <32>; dma-channel-mm2s { |