Merge tag 'pci-v7.2-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull pci updates from Bjorn Helgaas:
 "Enumeration:

   - Remove MPS/MRRS Kconfig settings (CONFIG_PCIE_BUS_*) that worked
     around a WiFi device defect; use a quirk or boot-time
     "pci=pcie_bus_tune_*" kernel parameter instead (Bjorn Helgaas)

   - Always lift 2.5GT/s restriction in PCIe failed link retraining to
     avoid clamping a link to 2.5GT/s after hot-plug changes the device
     (Maciej W. Rozycki)

   - Request bus reassignment when not probe-only to fix an enumeration
     regression on Marvell CN106XX and possibly other DT-based systems
     (Ratheesh Kannoth)

   - Fix procfs race between pci_proc_init() and pci_bus_add_device()
     that resulted in 'proc_dir_entry ... already registered' warnings
     and pointer corruption (Krzysztof Wilczyński)

   - Fix sysfs race that causes 'duplicate filename' warnings and boot
     panics by converting PCI resource files to static attributes
     (Krzysztof Wilczyński)

   - Expose sysfs 'resourceN_resize' attributes only on platforms with
     PCI mmap (Krzysztof Wilczyński)

   - Require CAP_SYS_ADMIN to write to sysfs 'resourceN_resize'
     attributes (Krzysztof Wilczyński)

   - Add security_locked_down(LOCKDOWN_PCI_ACCESS) to alpha PCI resource
     mmap path to match the generic path (Krzysztof Wilczyński)

   - Use kstrtobool() to parse the 'rom' attribute input to avoid the
     unexpected behavior of enabling the ROM when writing '0' with no
     trailing newline (Krzysztof Wilczyński)

  Resource management:

   - Improve resource claim logging for debuggability (Ilpo Järvinen)

   - Clean up several uses of const parameters (Ilpo Järvinen)

   - Check option ROM header signatures and lengths before accessing to
     avoid page faults and alignment faults (Guixin Liu)

  ASPM:

   - Don't reconfigure ASPM when entering low-power D-state; only do it
     when returning back to D0 (Carlos Bilbao)

  Power management:

   - During suspend, set power state to 'unknown' for all devices, not
     just those with drivers (Lukas Wunner)

   - Skip restoring Resizable BARs and VF Resizable BARs if device
     doesn't respond to config reads, to avoid invalid array accesses
     (Marco Nenciarini)

   - Add pci_suspend_retains_context() so drivers can tell whether
     devices retain internal state across suspend/resume, since some
     platforms reset devices on suspend; use this in nvme to avoid
     issues on Qcom RCs (Manivannan Sadhasivam)

  Power control:

   - Only to power on/off devices that actually support power control to
     avoid poking at incompatible devices mentioned in DT (Manivannan
     Sadhasivam)

  Virtualization and resets:

   - Log device readiness timeouts as errors, not warnings, because the
     device is likely unusable in this case (Bjorn Helgaas)

   - Wait for device readiness after soft reset (D3hot ->
     D0uninitialized transition), when the device may respond with
     Request Retry Status (RRS) if it needs more time to initialize
     (Bjorn Helgaas)

   - Drop unnecessary retries when restoring BARs because resets should
     now already include all required delays (Lukas Wunner)

   - Avoid FLR for MediaTek MT7925 WiFi, where FLR fails after a VM
     terminates uncleanly (Jose Ignacio Tornos Martinez)

   - Avoid SBR for Qualcomm WCN6855/WCN7850 WiFi, SDX62/SDX65 modems,
     which seem not to support it correctly (Jose Ignacio Tornos
     Martinez)

  Peer-to-peer DMA:

   - Prevent P2PDMA as well as CPU access to non-mappable BARs, e.g.,
     s390 ISM BARs (Matt Evans)

   - Add Intel QAT, DSA, IAA devices to whitelist (Lukas Wunner)

  Endpoint framework:

   - Add endpoint controller APIs for use by function drivers to
     discover auxiliary blocks like DMA engines (Koichiro Den)

   - Remember DesignWare eDMA engine base/size and expose them via the
     EPC aux-resource API (Koichiro Den)

   - Add endpoint embedded doorbell fallback, used if MSI allocation
     fails (Koichiro Den)

   - Validate BAR index and remove dead BAR read in endpoint doorbell
     test (Carlos Bilbao)

   - Unwind MSI/MSI-X vectors if NTB initialization fails part-way
     through (Koichiro Den)

   - Cache sleepable pci_irq_vector() value at ISR setup to avoid
     calling it from hardirq context (Koichiro Den)

   - Call sleepable pci_epc_raise_irq() from a work item instead of
     atomic context, e.g., when setting bits in NTB peer doorbells in
     the ntb_peer_db_set() path (Koichiro Den)

   - Report 0-based vNTB doorbell vector to account for link event 0 and
     historically skipped slot 1 (Koichiro Den)

   - Prevent configfs writes to vNTB db_count and other values that are
     already in use after EPC attach (Koichiro Den)

   - Account for vNTB db_valid reserved slots (link event 0 and
     historically skipped slot 1) so they don't appear as valid
     doorbells (Koichiro Den)

   - Implement vNTB .db_vector_count()/mask() for doorbells so clients
     can use multiple vectors and avoid thundering herds (Koichiro Den)

   - Report 0-based NTB doorbell vector to account for link event 0 and
     historically skipped slot 1 (Koichiro Den)

   - Fix doorbell bitmask and IRQ vector handling to clear only
     specified bits, use the correct vector for non-contiguous Linux IRQ
     numbers, and validate incoming vectors (Koichiro Den)

   - Implement NTB .db_vector_count()/mask() for doorbells so clients
     can use multiple vectors (Koichiro Den)

  Native PCIe controller infrastructure:

   - Add pci_host_common_link_train_delay() for the mandatory delay
     after > 5GT/s Link training completes and use it for cadence HPA,
     j721e, LGA; dwc; aardvark, mediatek-gen3, rzg3s (Hans Zhang)

   - Protect root bus removal with rescan lock in altera, brcmstb,
     cadence, dwc, iproc, mediatek, plda, rockchip to prevent
     use-after-free or crashes when racing with sysfs rescan or hotplug
     (Hans Zhang)

   - Add pci_host_common_parse_ports() for use by any native driver to
     parse Root Port properties (per-Link features like width, speed,
     PHY, power and reset control, etc should be described in Root Port
     stanzas, not the host bridge; currently only reset GPIOs
     implemented) (Sherry Sun)

  New native PCIe controller drivers:

   - Add DT binding and driver for UltraRISC DP1000 PCIe controller
     (Xincheng Zhang, Jia Wang)

  Altera PCIe controller driver:

   - Do not dispose of the parent IRQ mapping, which belongs to the
     parent interrupt controller (Mahesh Vaidya)

   - Fix chained IRQ handler ordering issue and resource leaks on probe
     failure (Mahesh Vaidya)

  AMD MDB PCIe controller driver:

   - Assert PERST# on shutdown so any connected Endpoints are held in
     reset during shutdown (Sai Krishna Musham)

  Amlogic Meson PCIe controller driver:

   - Propagate devm_add_action_or_reset() failure to fix probe error
     path (Shuvam Pandey)

   - Add .remove() callback to deinitialize the host bridge and power
     off the PHY (Shuvam Pandey)

  Broadcom iProc PCIe controller driver:

   - Restore .map_irq() assignment; its removal broke INTx on the iproc
     platform bus driver (Mark Tomlinson)

  Broadcom STB PCIe controller driver:

   - No change, but products using certain WiFi devices may be affected
     by removal of CONFIG_PCIE_BUS_* (see above)

  Freescale i.MX6 PCIe controller driver:

   - Move IMX6SX_GPR12_PCIE_TEST_POWERDOWN handling into the core reset
     functions (Richard Zhu)

   - Assert PERST# before enabling regulators to ensure that even if
     power is enabled, endpoint stays inactive until REFCLK is stable
     (Sherry Sun)

   - Parse reset properties in Root Port nodes (falling back to host
     bridge) to help support Key E connectors and the pwrctrl framework
     (Sherry Sun)

   - Configure i.MX95 REF_USE_PAD before PHY reset (Richard Zhu)

   - Assert i.MX95 ref_clk_en after reference clock stabilizes (Richard
     Zhu)

   - Integrate new pwrctrl API for DTs with Root Port-level power
     supplies (Sherry Sun)

  Intel Gateway PCIe controller driver:

   - Enable clock before PHY init for correct ordering (Florian Eckert)

   - Add .start_link() callback so the driver works again (Florian
     Eckert)

   - Stop overwriting the ATU base address discovered by
     dw_pcie_get_resources() (Florian Eckert)

   - Add DT 'atu' region since this is hardware-specific, and fall back
     to driver default if lacking (Florian Eckert)

  Loongson PCIe controller driver:

   - Ignore downstream devices only on internal bridges to avoid
     Loongson hardware issue (Rong Zhang)

   - Quirk old Loongson-3C6000 bridges that advertise incorrect
     supported link speeds (Ziyao Li)

  Marvell MVEBU PCIe controller driver:

   - Use fixed-width interrupt masks to avoid truncation in 64-bit
     builds (Rosen Penev)

  MediaTek PCIe controller driver:

   - Use FIELD_PREP() to fix incorrect operator precedence in
     PCIE_FTS_NUM_L0 (Li RongQing)

   - Fix IRQ domain leak when port fails to enable (Manivannan
     Sadhasivam)

   - Use actual physical address for MSI message address instead of
     virt_to_phys() (Manivannan Sadhasivam)

   - Add EcoNet EN7528 to DT binding (Caleb James DeLisle)

  MediaTek PCIe Gen3 controller driver:

   - Deassert PCIE_PHY_RSTB so REFCLK is stable for at least 100ms
     (PCIE_T_PVPERL_MS) before deasserting PERST# (Jian Yang)

   - Add .shutdown() to assert PERST# before powering down device (Jian
     Yang)

   - Do full device power down on removal, including asserting PERST#,
     when removing driver (Chen-Yu Tsai)

   - Fix a 'failed to create pwrctrl devices' error message that was
     inadvertently skipped (Chen-Yu Tsai)

  NVIDIA Tegra194 PCIe controller driver:

   - Program the DesignWare PORT_AFR L1 entrance latency based on the
     'aspm-l1-entry-delay-ns' DT property (Manikanta Maddireddy)

  Qualcomm PCIe controller driver:

   - Add Eliza SoC compatible in DT binding (Krishna Chaitanya Chundru)

   - Set max OPP during resume so DBI register accesses don't fail with
     NoC errors (Qiang Yu)

   - Add pci_host_common_d3cold_possible() to determine whether
     downstream devices are already in D3hot and wakeup-enabled devices
     are capable of generating PME from D3cold (Krishna Chaitanya
     Chundru)

   - Add .get_ltssm() callback to get the LTSSM status without DBI,
     since DBI may be inaccessible after PME_Turn_Off (Krishna Chaitanya
     Chundru)

   - Power down PHY via PARF_PHY_CTRL before disabling rails/clocks to
     avoid power leakage (Krishna Chaitanya Chundru)

   - Decide whether suspend should put the link in L2 and power down
     using pci_host_common_d3cold_possible() instead of checking whether
     ASPM L1 is enabled (Krishna Chaitanya Chundru)

   - Add qcom D3cold support to tear down interconnect bandwidth and OPP
     votes (Krishna Chaitanya Chundru)

   - Handle unsupported mixed PERST#/PHY DT configurations, e.g., PHY in
     RP node while PERST# is in the RC node, but warn about the DT issue
     (Qiang Yu)

   - Program T_POWER_ON based on DT 't-power-on-us' property in case
     hardware advertises incorrect values (Krishna Chaitanya Chundru)

   - Disable ASPM L0s for SA8775P (Shawn Guo)

   - Initialize DWC MSI lock for firmware-managed ECAM hosts, which
     don't use the dw_pcie_host_init() path that initializes the lock
     (Yadu M G)

  Renesas RZ/G3S PCIe controller driver:

   - Add RZ/V2N DT support (Lad Prabhakar)

  SOPHGO PCIe controller driver:

   - Add 'dma-coherent' DT property for sg2042-pcie driver (Han Gao)

  Synopsys DesignWare PCIe controller driver:

   - Apply ECRC TLP Digest workaround for all DesignWare cores prior to
     5.10a, not just 4.90a and 5.00a (Manikanta Maddireddy)

   - Use common struct dw_pcie 'mode' rather than duplicating it in
     artpec6, dra7xx, dwc-pcie, and keembay driver structs (Hans Zhang)

   - Use DEFINE_SHOW_ATTRIBUTE for ltssm_status debugfs to reduce
     boilerplate and fix a seq_file memory leak by including a
     .release() callback (Hans Zhang)

   - Fix a signedness bug in fault injection test code (Dan Carpenter)

   - Avoid NULL pointer dereference when tearing down debugfs for
     controller that lacks RAS DES capability (Shuvam Pandey)

  MicroSemi Switchtec management driver:

   - Add Gen6 Device IDs (Ben Reed)

  Miscellaneous:

   - Remove unused gpio.h include from amd-mdb, designware-plat, fu740,
     visconti drivers (Andy Shevchenko)

   - Fix typos in documentation (josh ziegler)

   - Use FIELD_MODIFY() instead of open-coding it (Hans Zhang)"

* tag 'pci-v7.2-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (168 commits)
  PCI/sysfs: Use kstrtobool() to parse the ROM attribute input
  PCI/sysfs: Limit BAR resize attribute scope to platforms with PCI mmap
  PCI/sysfs: Remove pci_create_legacy_files() and pci_sysfs_init()
  PCI/sysfs: Convert legacy I/O and memory attributes to static definitions
  PCI/sysfs: Add __weak pci_legacy_has_sparse() helper
  alpha/PCI: Compute legacy size in pci_mmap_legacy_page_range()
  PCI: Add macros for legacy I/O and memory address space sizes
  PCI/sysfs: Remove pci_{create,remove}_sysfs_dev_files()
  alpha/PCI: Convert resource files to static attributes
  alpha/PCI: Add static PCI resource attribute macros
  alpha/PCI: Remove WARN from __pci_mmap_fits() and __legacy_mmap_fits()
  alpha/PCI: Fix __pci_mmap_fits() overflow for zero-length BARs
  alpha/PCI: Use PCI resource accessor macros
  alpha/PCI: Use BAR index in sysfs attr->private instead of resource pointer
  alpha/PCI: Add security_locked_down() check to pci_mmap_resource()
  PCI/sysfs: Limit pci_sysfs_init() late_initcall compile scope
  PCI/sysfs: Add stubs for pci_{create,remove}_sysfs_dev_files()
  PCI/sysfs: Warn about BAR resize failure in __resource_resize_store()
  PCI/sysfs: Convert PCI resource files to static attributes
  PCI/proc: Fix race between pci_proc_init() and pci_bus_add_device()
  ...

7 files changed, 226 insertions, 10 deletions

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index 9d1349855b42..e8b8131f5f23 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -66,16 +66,34 @@ properties:
       - const: dma
 
   reset-gpio:
+    deprecated: true
     description: Should specify the GPIO for controlling the PCI bus device
       reset signal. It's not polarity aware and defaults to active-low reset
       sequence (L=reset state, H=operation state) (optional required).
+      This property is deprecated, instead of referencing this property from the
+      host bridge node, use the reset-gpios property from the root port node.
 
   reset-gpio-active-high:
+    deprecated: true
     description: If present then the reset sequence using the GPIO
       specified in the "reset-gpio" property is reversed (H=reset state,
       L=operation state) (optional required).
+      This property is deprecated along with the reset-gpio property above, use
+      the reset-gpios property from the root port node.
     type: boolean
 
+  pcie@0:
+    description:
+      Describe the i.MX6 PCIe Root Port.
+    type: object
+    $ref: /schemas/pci/pci-pci-bridge.yaml#
+
+    properties:
+      reg:
+        maxItems: 1
+
+    unevaluatedProperties: false
+
 required:
   - compatible
   - reg
@@ -236,6 +254,7 @@ unevaluatedProperties: false
 examples:
   - |
     #include <dt-bindings/clock/imx6qdl-clock.h>
+    #include <dt-bindings/gpio/gpio.h>
     #include <dt-bindings/interrupt-controller/arm-gic.h>
 
     pcie: pcie@1ffc000 {
@@ -262,5 +281,18 @@ examples:
                 <&clks IMX6QDL_CLK_LVDS1_GATE>,
                 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
         clock-names = "pcie", "pcie_bus", "pcie_phy";
+
+        pcie_port0: pcie@0 {
+            compatible = "pciclass,0604";
+            device_type = "pci";
+            reg = <0x0 0x0 0x0 0x0 0x0>;
+            bus-range = <0x01 0xff>;
+
+            #address-cells = <3>;
+            #size-cells = <2>;
+            ranges;
+
+            reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+        };
     };
 ...
diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
index 54e2890ae631..394bb46b38e6 100644
--- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml
@@ -27,16 +27,20 @@ properties:
       - const: snps,dw-pcie
 
   reg:
+    minItems: 3
     items:
       - description: Controller control and status registers.
       - description: PCIe configuration registers.
       - description: Controller application registers.
+      - description: Internal Address Translation Unit (iATU) registers.
 
   reg-names:
+    minItems: 3
     items:
       - const: dbi
       - const: config
       - const: app
+      - const: atu
 
   ranges:
     maxItems: 1
@@ -95,8 +99,9 @@ examples:
       #size-cells = <2>;
       reg = <0xd0e00000 0x1000>,
             <0xd2000000 0x800000>,
-            <0xd0a41000 0x1000>;
-      reg-names = "dbi", "config", "app";
+            <0xd0a41000 0x1000>,
+            <0xd0ec0000 0x1000>;
+      reg-names = "dbi", "config", "app", "atu";
       linux,pci-domain = <0>;
       max-link-speed = <4>;
       bus-range = <0x00 0x08>;
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
index 0b8c78ec4f91..c009a7a52bc6 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml
@@ -14,6 +14,7 @@ properties:
     oneOf:
       - enum:
           - airoha,an7583-pcie
+          - econet,en7528-pcie
           - mediatek,mt2712-pcie
           - mediatek,mt7622-pcie
           - mediatek,mt7629-pcie
@@ -226,6 +227,31 @@ allOf:
 
         mediatek,pbus-csr: false
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: econet,en7528-pcie
+    then:
+      properties:
+        clocks:
+          maxItems: 1
+
+        clock-names:
+          maxItems: 1
+
+        resets: false
+
+        reset-names: false
+
+        power-domains: false
+
+        mediatek,pbus-csr: false
+
+      required:
+        - phys
+        - phy-names
+
 unevaluatedProperties: false
 
 examples:
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
index 3a94a9c1bb15..fb706b1397a3 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml
@@ -20,6 +20,7 @@ properties:
       - const: qcom,pcie-sm8550
       - items:
           - enum:
+              - qcom,eliza-pcie
               - qcom,kaanapali-pcie
               - qcom,sar2130p-pcie
               - qcom,pcie-sm8650
@@ -91,6 +92,55 @@ required:
 
 allOf:
   - $ref: qcom,pcie-common.yaml#
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,eliza-pcie
+    then:
+      properties:
+        reg:
+          minItems: 6
+        reg-names:
+          minItems: 6
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,eliza-pcie
+    then:
+      properties:
+        clocks:
+          minItems: 8
+          maxItems: 8
+        clock-names:
+          minItems: 8
+          maxItems: 8
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,eliza-pcie
+    then:
+      properties:
+        interrupts:
+          minItems: 9
+        interrupt-names:
+          minItems: 9
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: qcom,eliza-pcie
+    then:
+      properties:
+        resets:
+          minItems: 2
+        reset-names:
+          minItems: 2
 
 unevaluatedProperties: false
 
diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
index a67108c48feb..90086909e921 100644
--- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml
@@ -4,21 +4,27 @@
 $id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Renesas RZ/G3S PCIe host controller
+title: Renesas RZ/G3S PCIe host controller (and similar SoCs)
 
 maintainers:
   - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
 
-description:
-  Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe
-  Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and
-  up to 8 GT/s (Gen3) for RZ/G3E.
+description: |
+  PCIe host controller found in Renesas RZ/G3S and similar SoCs complies
+  with PCIe Base Specification 4.0 and supports different link speeds
+  depending on the SoC variant:
+    - Gen2 (5 GT/s): RZ/G3S
+    - Gen3 (8 GT/s): RZ/G3E, RZ/V2N
 
 properties:
   compatible:
-    enum:
-      - renesas,r9a08g045-pcie # RZ/G3S
-      - renesas,r9a09g047-pcie # RZ/G3E
+    oneOf:
+      - enum:
+          - renesas,r9a08g045-pcie # RZ/G3S
+          - renesas,r9a09g047-pcie # RZ/G3E
+      - items:
+          - const: renesas,r9a09g056-pcie # RZ/V2N
+          - const: renesas,r9a09g047-pcie
 
   reg:
     maxItems: 1
@@ -152,6 +158,7 @@ patternProperties:
         enum:
           - 0x0033
           - 0x0039
+          - 0x003b
 
       clocks:
         items:
diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
index f8b7ca57fff1..ab482488b047 100644
--- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
@@ -30,6 +30,8 @@ properties:
   device-id:
     const: 0x2042
 
+  dma-coherent: true
+
   msi-parent: true
 
 allOf:
@@ -60,5 +62,6 @@ examples:
       vendor-id = <0x1f1c>;
       device-id = <0x2042>;
       cdns,no-bar-match-nbits = <48>;
+      dma-coherent;
       msi-parent = <&msi>;
     };
diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
new file mode 100644
index 000000000000..512b935bf5d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: UltraRISC DP1000 PCIe Host Controller
+
+description:
+  UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
+
+maintainers:
+  - Xincheng Zhang <zhangxincheng@ultrarisc.com>
+  - Jia Wang <wangjia@ultrarisc.com>
+
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+properties:
+  compatible:
+    const: ultrarisc,dp1000-pcie
+
+  reg:
+    items:
+      - description: Data Bus Interface (DBI) registers.
+      - description: PCIe configuration space region.
+
+  reg-names:
+    items:
+      - const: dbi
+      - const: config
+
+  num-lanes:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    enum: [4, 16]
+    description: Number of lanes to use.
+
+  interrupts:
+    items:
+      - description: MSI interrupt
+      - description: Legacy INTA interrupt
+      - description: Legacy INTB interrupt
+      - description: Legacy INTC interrupt
+      - description: Legacy INTD interrupt
+
+  interrupt-names:
+    items:
+      - const: msi
+      - const: inta
+      - const: intb
+      - const: intc
+      - const: intd
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - interrupts
+  - interrupt-names
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      pcie@21000000 {
+        compatible = "ultrarisc,dp1000-pcie";
+        reg = <0x0 0x21000000 0x0 0x01000000>,
+              <0x0 0x4fff0000 0x0 0x00010000>;
+        reg-names = "dbi", "config";
+        ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,
+                 <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,
+                 <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        #interrupt-cells = <1>;
+        device_type = "pci";
+        dma-coherent;
+        bus-range = <0x0 0xff>;
+        num-lanes = <16>;
+        interrupt-parent = <&plic>;
+        interrupts = <43>, <44>, <45>, <46>, <47>;
+        interrupt-names = "msi", "inta", "intb", "intc", "intd";
+        interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+        interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
+                        <0x0 0x0 0x0 0x2 &plic 45>,
+                        <0x0 0x0 0x0 0x3 &plic 46>,
+                        <0x0 0x0 0x0 0x4 &plic 47>;
+      };
+    };