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| author | Mark Brown <broonie@kernel.org> | 2026-10-01 13:48:22 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-10-01 13:48:22 +0100 |
| commit | ff8b4030161b58be72d756337bf0e1c8ce21a97c (patch) | |
| tree | e304424ab6245a1ab409e4f0994f929c61c75bf1 | |
| parent | d1d38455235370e4e5f02e84d3f197d57129977c (diff) | |
| parent | 11430072551f5d5a37f58e390b3d042035992ca4 (diff) | |
| download | linux-next-ff8b4030161b58be72d756337bf0e1c8ce21a97c.tar.gz linux-next-ff8b4030161b58be72d756337bf0e1c8ce21a97c.zip | |
Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git
24 files changed, 973 insertions, 429 deletions
diff --git a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml index 02f0b0462377..bf9923b63852 100644 --- a/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml +++ b/Documentation/devicetree/bindings/fuse/nvidia,tegra20-fuse.yaml @@ -22,6 +22,7 @@ properties: - nvidia,tegra186-efuse - nvidia,tegra194-efuse - nvidia,tegra234-efuse + - nvidia,tegra264-efuse - items: - const: nvidia,tegra132-efuse diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index 9398aae49093..8e0c67d671f9 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -16,9 +16,13 @@ description: | properties: compatible: - enum: - - nvidia,tegra114-emc - - nvidia,tegra124-emc + oneOf: + - enum: + - nvidia,tegra114-emc + - nvidia,tegra124-emc + - items: + - const: nvidia,tegra132-emc + - const: nvidia,tegra124-emc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index f8747cebb680..2f1ffd27e1d9 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -22,6 +22,7 @@ properties: enum: - nvidia,tegra114-mc - nvidia,tegra124-mc + - nvidia,tegra132-mc reg: maxItems: 1 diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvidia/tegra124.dtsi index ce4efa1de509..86956b94ca0b 100644 --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi @@ -1114,13 +1114,13 @@ "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", "rx9", "tx9"; - ranges; - #address-cells = <2>; - #size-cells = <2>; + ranges = <0x70300000 0x0 0x70300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; tegra_i2s0: i2s@70301000 { compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301000 0x0 0x100>; + reg = <0x70301000 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks = <&tegra_car TEGRA124_CLK_I2S0>; resets = <&tegra_car 30>; @@ -1130,7 +1130,7 @@ tegra_i2s1: i2s@70301100 { compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301100 0x0 0x100>; + reg = <0x70301100 0x100>; nvidia,ahub-cif-ids = <5 5>; clocks = <&tegra_car TEGRA124_CLK_I2S1>; resets = <&tegra_car 11>; @@ -1140,7 +1140,7 @@ tegra_i2s2: i2s@70301200 { compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301200 0x0 0x100>; + reg = <0x70301200 0x100>; nvidia,ahub-cif-ids = <6 6>; clocks = <&tegra_car TEGRA124_CLK_I2S2>; resets = <&tegra_car 18>; @@ -1150,7 +1150,7 @@ tegra_i2s3: i2s@70301300 { compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301300 0x0 0x100>; + reg = <0x70301300 0x100>; nvidia,ahub-cif-ids = <7 7>; clocks = <&tegra_car TEGRA124_CLK_I2S3>; resets = <&tegra_car 101>; @@ -1160,7 +1160,7 @@ tegra_i2s4: i2s@70301400 { compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301400 0x0 0x100>; + reg = <0x70301400 0x100>; nvidia,ahub-cif-ids = <8 8>; clocks = <&tegra_car TEGRA124_CLK_I2S4>; resets = <&tegra_car 102>; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 26cd11a8a4a1..3463fa637b37 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -936,13 +936,13 @@ "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", "rx9", "tx9"; - ranges; - #address-cells = <2>; - #size-cells = <2>; + ranges = <0x70300000 0x0 0x70300000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; tegra_i2s0: i2s@70301000 { compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301000 0x0 0x100>; + reg = <0x70301000 0x100>; nvidia,ahub-cif-ids = <4 4>; clocks = <&tegra_car TEGRA124_CLK_I2S0>; clock-names = "i2s"; @@ -953,7 +953,7 @@ tegra_i2s1: i2s@70301100 { compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301100 0x0 0x100>; + reg = <0x70301100 0x100>; nvidia,ahub-cif-ids = <5 5>; clocks = <&tegra_car TEGRA124_CLK_I2S1>; clock-names = "i2s"; @@ -964,7 +964,7 @@ tegra_i2s2: i2s@70301200 { compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301200 0x0 0x100>; + reg = <0x70301200 0x100>; nvidia,ahub-cif-ids = <6 6>; clocks = <&tegra_car TEGRA124_CLK_I2S2>; clock-names = "i2s"; @@ -975,7 +975,7 @@ tegra_i2s3: i2s@70301300 { compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301300 0x0 0x100>; + reg = <0x70301300 0x100>; nvidia,ahub-cif-ids = <7 7>; clocks = <&tegra_car TEGRA124_CLK_I2S3>; clock-names = "i2s"; @@ -986,7 +986,7 @@ tegra_i2s4: i2s@70301400 { compatible = "nvidia,tegra124-i2s"; - reg = <0x0 0x70301400 0x0 0x100>; + reg = <0x70301400 0x100>; nvidia,ahub-cif-ids = <8 8>; clocks = <&tegra_car TEGRA124_CLK_I2S4>; clock-names = "i2s"; diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts index d9aafe053112..4b2fa1a49f05 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dts @@ -1176,22 +1176,22 @@ }; cooling-maps { - cpu-critical { + map-critical { cooling-device = <&fan 3 3>; trip = <&cpu_trip_critical>; }; - cpu-hot { + map-hot { cooling-device = <&fan 2 2>; trip = <&cpu_trip_hot>; }; - cpu-active { + map-active { cooling-device = <&fan 1 1>; trip = <&cpu_trip_active>; }; - cpu-passive { + map-passive { cooling-device = <&fan 0 0>; trip = <&cpu_trip_passive>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 705af0373a09..623d5e654323 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -142,15 +142,15 @@ assigned-clocks = <&bpmp TEGRA186_CLK_AHUB>; assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>; assigned-clock-rates = <81600000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900000 0x0 0x02900000 0x20000>; status = "disabled"; tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901000 0x0 0x100>; + reg = <0x2901000 0x100>; clocks = <&bpmp TEGRA186_CLK_I2S1>, <&bpmp TEGRA186_CLK_I2S1_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -164,7 +164,7 @@ tegra_i2s2: i2s@2901100 { compatible = "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901100 0x0 0x100>; + reg = <0x2901100 0x100>; clocks = <&bpmp TEGRA186_CLK_I2S2>, <&bpmp TEGRA186_CLK_I2S2_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -178,7 +178,7 @@ tegra_i2s3: i2s@2901200 { compatible = "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901200 0x0 0x100>; + reg = <0x2901200 0x100>; clocks = <&bpmp TEGRA186_CLK_I2S3>, <&bpmp TEGRA186_CLK_I2S3_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -192,7 +192,7 @@ tegra_i2s4: i2s@2901300 { compatible = "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901300 0x0 0x100>; + reg = <0x2901300 0x100>; clocks = <&bpmp TEGRA186_CLK_I2S4>, <&bpmp TEGRA186_CLK_I2S4_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -206,7 +206,7 @@ tegra_i2s5: i2s@2901400 { compatible = "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901400 0x0 0x100>; + reg = <0x2901400 0x100>; clocks = <&bpmp TEGRA186_CLK_I2S5>, <&bpmp TEGRA186_CLK_I2S5_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -220,7 +220,7 @@ tegra_i2s6: i2s@2901500 { compatible = "nvidia,tegra186-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901500 0x0 0x100>; + reg = <0x2901500 0x100>; clocks = <&bpmp TEGRA186_CLK_I2S6>, <&bpmp TEGRA186_CLK_I2S6_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -234,7 +234,7 @@ tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902000 0x0 0x200>; + reg = <0x2902000 0x200>; sound-name-prefix = "SFC1"; status = "disabled"; }; @@ -242,7 +242,7 @@ tegra_sfc2: sfc@2902200 { compatible = "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902200 0x0 0x200>; + reg = <0x2902200 0x200>; sound-name-prefix = "SFC2"; status = "disabled"; }; @@ -250,7 +250,7 @@ tegra_sfc3: sfc@2902400 { compatible = "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902400 0x0 0x200>; + reg = <0x2902400 0x200>; sound-name-prefix = "SFC3"; status = "disabled"; }; @@ -258,7 +258,7 @@ tegra_sfc4: sfc@2902600 { compatible = "nvidia,tegra186-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902600 0x0 0x200>; + reg = <0x2902600 0x200>; sound-name-prefix = "SFC4"; status = "disabled"; }; @@ -266,7 +266,7 @@ tegra_amx1: amx@2903000 { compatible = "nvidia,tegra186-amx", "nvidia,tegra210-amx"; - reg = <0x0 0x2903000 0x0 0x100>; + reg = <0x2903000 0x100>; sound-name-prefix = "AMX1"; status = "disabled"; }; @@ -274,7 +274,7 @@ tegra_amx2: amx@2903100 { compatible = "nvidia,tegra186-amx", "nvidia,tegra210-amx"; - reg = <0x0 0x2903100 0x0 0x100>; + reg = <0x2903100 0x100>; sound-name-prefix = "AMX2"; status = "disabled"; }; @@ -282,7 +282,7 @@ tegra_amx3: amx@2903200 { compatible = "nvidia,tegra186-amx", "nvidia,tegra210-amx"; - reg = <0x0 0x2903200 0x0 0x100>; + reg = <0x2903200 0x100>; sound-name-prefix = "AMX3"; status = "disabled"; }; @@ -290,7 +290,7 @@ tegra_amx4: amx@2903300 { compatible = "nvidia,tegra186-amx", "nvidia,tegra210-amx"; - reg = <0x0 0x2903300 0x0 0x100>; + reg = <0x2903300 0x100>; sound-name-prefix = "AMX4"; status = "disabled"; }; @@ -298,7 +298,7 @@ tegra_adx1: adx@2903800 { compatible = "nvidia,tegra186-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903800 0x0 0x100>; + reg = <0x2903800 0x100>; sound-name-prefix = "ADX1"; status = "disabled"; }; @@ -306,7 +306,7 @@ tegra_adx2: adx@2903900 { compatible = "nvidia,tegra186-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903900 0x0 0x100>; + reg = <0x2903900 0x100>; sound-name-prefix = "ADX2"; status = "disabled"; }; @@ -314,7 +314,7 @@ tegra_adx3: adx@2903a00 { compatible = "nvidia,tegra186-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903a00 0x0 0x100>; + reg = <0x2903a00 0x100>; sound-name-prefix = "ADX3"; status = "disabled"; }; @@ -322,14 +322,14 @@ tegra_adx4: adx@2903b00 { compatible = "nvidia,tegra186-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903b00 0x0 0x100>; + reg = <0x2903b00 0x100>; sound-name-prefix = "ADX4"; status = "disabled"; }; tegra_dmic1: dmic@2904000 { compatible = "nvidia,tegra210-dmic"; - reg = <0x0 0x2904000 0x0 0x100>; + reg = <0x2904000 0x100>; clocks = <&bpmp TEGRA186_CLK_DMIC1>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA186_CLK_DMIC1>; @@ -341,7 +341,7 @@ tegra_dmic2: dmic@2904100 { compatible = "nvidia,tegra210-dmic"; - reg = <0x0 0x2904100 0x0 0x100>; + reg = <0x2904100 0x100>; clocks = <&bpmp TEGRA186_CLK_DMIC2>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA186_CLK_DMIC2>; @@ -353,7 +353,7 @@ tegra_dmic3: dmic@2904200 { compatible = "nvidia,tegra210-dmic"; - reg = <0x0 0x2904200 0x0 0x100>; + reg = <0x2904200 0x100>; clocks = <&bpmp TEGRA186_CLK_DMIC3>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA186_CLK_DMIC3>; @@ -365,7 +365,7 @@ tegra_dmic4: dmic@2904300 { compatible = "nvidia,tegra210-dmic"; - reg = <0x0 0x2904300 0x0 0x100>; + reg = <0x2904300 0x100>; clocks = <&bpmp TEGRA186_CLK_DMIC4>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA186_CLK_DMIC4>; @@ -377,7 +377,7 @@ tegra_dspk1: dspk@2905000 { compatible = "nvidia,tegra186-dspk"; - reg = <0x0 0x2905000 0x0 0x100>; + reg = <0x2905000 0x100>; clocks = <&bpmp TEGRA186_CLK_DSPK1>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA186_CLK_DSPK1>; @@ -389,7 +389,7 @@ tegra_dspk2: dspk@2905100 { compatible = "nvidia,tegra186-dspk"; - reg = <0x0 0x2905100 0x0 0x100>; + reg = <0x2905100 0x100>; clocks = <&bpmp TEGRA186_CLK_DSPK2>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA186_CLK_DSPK2>; @@ -402,9 +402,9 @@ tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra186-ope", "nvidia,tegra210-ope"; - reg = <0x0 0x2908000 0x0 0x100>; - #address-cells = <2>; - #size-cells = <2>; + reg = <0x2908000 0x100>; + #address-cells = <1>; + #size-cells = <1>; ranges; sound-name-prefix = "OPE1"; status = "disabled"; @@ -412,20 +412,20 @@ equalizer@2908100 { compatible = "nvidia,tegra186-peq", "nvidia,tegra210-peq"; - reg = <0x0 0x2908100 0x0 0x100>; + reg = <0x2908100 0x100>; }; dynamic-range-compressor@2908200 { compatible = "nvidia,tegra186-mbdrc", "nvidia,tegra210-mbdrc"; - reg = <0x0 0x2908200 0x0 0x200>; + reg = <0x2908200 0x200>; }; }; tegra_mvc1: mvc@290a000 { compatible = "nvidia,tegra186-mvc", "nvidia,tegra210-mvc"; - reg = <0x0 0x290a000 0x0 0x200>; + reg = <0x290a000 0x200>; sound-name-prefix = "MVC1"; status = "disabled"; }; @@ -433,7 +433,7 @@ tegra_mvc2: mvc@290a200 { compatible = "nvidia,tegra186-mvc", "nvidia,tegra210-mvc"; - reg = <0x0 0x290a200 0x0 0x200>; + reg = <0x290a200 0x200>; sound-name-prefix = "MVC2"; status = "disabled"; }; @@ -441,14 +441,14 @@ tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra186-amixer", "nvidia,tegra210-amixer"; - reg = <0x0 0x290bb00 0x0 0x800>; + reg = <0x290bb00 0x800>; sound-name-prefix = "MIXER1"; status = "disabled"; }; tegra_admaif: admaif@290f000 { compatible = "nvidia,tegra186-admaif"; - reg = <0x0 0x0290f000 0x0 0x1000>; + reg = <0x0290f000 0x1000>; dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, @@ -494,7 +494,7 @@ tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra186-asrc"; - reg = <0x0 0x2910000 0x0 0x2000>; + reg = <0x2910000 0x2000>; sound-name-prefix = "ASRC1"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 5462200f1176..478464464bcb 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -2450,22 +2450,22 @@ }; cooling-maps { - cpu-critical { + map-critical { cooling-device = <&fan 3 3>; trip = <&cpu_trip_critical>; }; - cpu-hot { + map-hot { cooling-device = <&fan 2 2>; trip = <&cpu_trip_hot>; }; - cpu-active { + map-active { cooling-device = <&fan 1 1>; trip = <&cpu_trip_active>; }; - cpu-passive { + map-passive { cooling-device = <&fan 0 0>; trip = <&cpu_trip_passive>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi index 6f4879c49da2..569d181b2ad2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p3509-0000.dtsi @@ -2433,22 +2433,22 @@ }; cooling-maps { - cpu-critical { + map-critical { cooling-device = <&fan 3 3>; trip = <&cpu_trip_critical>; }; - cpu-hot { + map-hot { cooling-device = <&fan 2 2>; trip = <&cpu_trip_hot>; }; - cpu-active { + map-active { cooling-device = <&fan 1 1>; trip = <&cpu_trip_active>; }; - cpu-passive { + map-passive { cooling-device = <&fan 0 0>; trip = <&cpu_trip_passive>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 5e510f77b538..13a95008c186 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -231,14 +231,14 @@ assigned-clock-rates = <81600000>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900000 0x0 0x02900000 0x20000>; tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901000 0x0 0x100>; + reg = <0x2901000 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S1>, <&bpmp TEGRA194_CLK_I2S1_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -252,7 +252,7 @@ tegra_i2s2: i2s@2901100 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901100 0x0 0x100>; + reg = <0x2901100 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S2>, <&bpmp TEGRA194_CLK_I2S2_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -266,7 +266,7 @@ tegra_i2s3: i2s@2901200 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901200 0x0 0x100>; + reg = <0x2901200 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S3>, <&bpmp TEGRA194_CLK_I2S3_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -280,7 +280,7 @@ tegra_i2s4: i2s@2901300 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901300 0x0 0x100>; + reg = <0x2901300 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S4>, <&bpmp TEGRA194_CLK_I2S4_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -294,7 +294,7 @@ tegra_i2s5: i2s@2901400 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901400 0x0 0x100>; + reg = <0x2901400 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S5>, <&bpmp TEGRA194_CLK_I2S5_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -308,7 +308,7 @@ tegra_i2s6: i2s@2901500 { compatible = "nvidia,tegra194-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901500 0x0 0x100>; + reg = <0x2901500 0x100>; clocks = <&bpmp TEGRA194_CLK_I2S6>, <&bpmp TEGRA194_CLK_I2S6_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -322,7 +322,7 @@ tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902000 0x0 0x200>; + reg = <0x2902000 0x200>; sound-name-prefix = "SFC1"; status = "disabled"; }; @@ -330,7 +330,7 @@ tegra_sfc2: sfc@2902200 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902200 0x0 0x200>; + reg = <0x2902200 0x200>; sound-name-prefix = "SFC2"; status = "disabled"; }; @@ -338,7 +338,7 @@ tegra_sfc3: sfc@2902400 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902400 0x0 0x200>; + reg = <0x2902400 0x200>; sound-name-prefix = "SFC3"; status = "disabled"; }; @@ -346,35 +346,35 @@ tegra_sfc4: sfc@2902600 { compatible = "nvidia,tegra194-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902600 0x0 0x200>; + reg = <0x2902600 0x200>; sound-name-prefix = "SFC4"; status = "disabled"; }; tegra_amx1: amx@2903000 { compatible = "nvidia,tegra194-amx"; - reg = <0x0 0x2903000 0x0 0x100>; + reg = <0x2903000 0x100>; sound-name-prefix = "AMX1"; status = "disabled"; }; tegra_amx2: amx@2903100 { compatible = "nvidia,tegra194-amx"; - reg = <0x0 0x2903100 0x0 0x100>; + reg = <0x2903100 0x100>; sound-name-prefix = "AMX2"; status = "disabled"; }; tegra_amx3: amx@2903200 { compatible = "nvidia,tegra194-amx"; - reg = <0x0 0x2903200 0x0 0x100>; + reg = <0x2903200 0x100>; sound-name-prefix = "AMX3"; status = "disabled"; }; tegra_amx4: amx@2903300 { compatible = "nvidia,tegra194-amx"; - reg = <0x0 0x2903300 0x0 0x100>; + reg = <0x2903300 0x100>; sound-name-prefix = "AMX4"; status = "disabled"; }; @@ -382,7 +382,7 @@ tegra_adx1: adx@2903800 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903800 0x0 0x100>; + reg = <0x2903800 0x100>; sound-name-prefix = "ADX1"; status = "disabled"; }; @@ -390,7 +390,7 @@ tegra_adx2: adx@2903900 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903900 0x0 0x100>; + reg = <0x2903900 0x100>; sound-name-prefix = "ADX2"; status = "disabled"; }; @@ -398,7 +398,7 @@ tegra_adx3: adx@2903a00 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903a00 0x0 0x100>; + reg = <0x2903a00 0x100>; sound-name-prefix = "ADX3"; status = "disabled"; }; @@ -406,7 +406,7 @@ tegra_adx4: adx@2903b00 { compatible = "nvidia,tegra194-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903b00 0x0 0x100>; + reg = <0x2903b00 0x100>; sound-name-prefix = "ADX4"; status = "disabled"; }; @@ -414,7 +414,7 @@ tegra_dmic1: dmic@2904000 { compatible = "nvidia,tegra194-dmic", "nvidia,tegra210-dmic"; - reg = <0x0 0x2904000 0x0 0x100>; + reg = <0x2904000 0x100>; clocks = <&bpmp TEGRA194_CLK_DMIC1>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA194_CLK_DMIC1>; @@ -427,7 +427,7 @@ tegra_dmic2: dmic@2904100 { compatible = "nvidia,tegra194-dmic", "nvidia,tegra210-dmic"; - reg = <0x0 0x2904100 0x0 0x100>; + reg = <0x2904100 0x100>; clocks = <&bpmp TEGRA194_CLK_DMIC2>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA194_CLK_DMIC2>; @@ -440,7 +440,7 @@ tegra_dmic3: dmic@2904200 { compatible = "nvidia,tegra194-dmic", "nvidia,tegra210-dmic"; - reg = <0x0 0x2904200 0x0 0x100>; + reg = <0x2904200 0x100>; clocks = <&bpmp TEGRA194_CLK_DMIC3>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA194_CLK_DMIC3>; @@ -453,7 +453,7 @@ tegra_dmic4: dmic@2904300 { compatible = "nvidia,tegra194-dmic", "nvidia,tegra210-dmic"; - reg = <0x0 0x2904300 0x0 0x100>; + reg = <0x2904300 0x100>; clocks = <&bpmp TEGRA194_CLK_DMIC4>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA194_CLK_DMIC4>; @@ -466,7 +466,7 @@ tegra_dspk1: dspk@2905000 { compatible = "nvidia,tegra194-dspk", "nvidia,tegra186-dspk"; - reg = <0x0 0x2905000 0x0 0x100>; + reg = <0x2905000 0x100>; clocks = <&bpmp TEGRA194_CLK_DSPK1>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA194_CLK_DSPK1>; @@ -479,7 +479,7 @@ tegra_dspk2: dspk@2905100 { compatible = "nvidia,tegra194-dspk", "nvidia,tegra186-dspk"; - reg = <0x0 0x2905100 0x0 0x100>; + reg = <0x2905100 0x100>; clocks = <&bpmp TEGRA194_CLK_DSPK2>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA194_CLK_DSPK2>; @@ -492,31 +492,31 @@ tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra194-ope", "nvidia,tegra210-ope"; - reg = <0x0 0x2908000 0x0 0x100>; + reg = <0x2908000 0x100>; sound-name-prefix = "OPE1"; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; ranges; equalizer@2908100 { compatible = "nvidia,tegra194-peq", "nvidia,tegra210-peq"; - reg = <0x0 0x2908100 0x0 0x100>; + reg = <0x2908100 0x100>; }; dynamic-range-compressor@2908200 { compatible = "nvidia,tegra194-mbdrc", "nvidia,tegra210-mbdrc"; - reg = <0x0 0x2908200 0x0 0x200>; + reg = <0x2908200 0x200>; }; }; tegra_mvc1: mvc@290a000 { compatible = "nvidia,tegra194-mvc", "nvidia,tegra210-mvc"; - reg = <0x0 0x290a000 0x0 0x200>; + reg = <0x290a000 0x200>; sound-name-prefix = "MVC1"; status = "disabled"; }; @@ -524,7 +524,7 @@ tegra_mvc2: mvc@290a200 { compatible = "nvidia,tegra194-mvc", "nvidia,tegra210-mvc"; - reg = <0x0 0x290a200 0x0 0x200>; + reg = <0x290a200 0x200>; sound-name-prefix = "MVC2"; status = "disabled"; }; @@ -532,7 +532,7 @@ tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra194-amixer", "nvidia,tegra210-amixer"; - reg = <0x0 0x290bb00 0x0 0x800>; + reg = <0x290bb00 0x800>; sound-name-prefix = "MIXER1"; status = "disabled"; }; @@ -540,7 +540,7 @@ tegra_admaif: admaif@290f000 { compatible = "nvidia,tegra194-admaif", "nvidia,tegra186-admaif"; - reg = <0x0 0x0290f000 0x0 0x1000>; + reg = <0x0290f000 0x1000>; dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, @@ -591,7 +591,7 @@ tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra194-asrc", "nvidia,tegra186-asrc"; - reg = <0x0 0x2910000 0x0 0x2000>; + reg = <0x2910000 0x2000>; sound-name-prefix = "ASRC1"; status = "disabled"; }; @@ -923,6 +923,8 @@ <&bpmp TEGRA194_CLK_QSPI0_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA194_RESET_QSPI0>; + dmas = <&gpcdma 5>, <&gpcdma 5>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -1013,6 +1015,8 @@ <&bpmp TEGRA194_CLK_QSPI1_PM>; clock-names = "qspi", "qspi_out"; resets = <&bpmp TEGRA194_RESET_QSPI1>; + dmas = <&gpcdma 6>, <&gpcdma 6>; + dma-names = "rx", "tx"; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index d78b9bd45df6..8ee334c10871 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -1750,7 +1750,7 @@ label = "Force Recovery"; gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; - linux,code = <BTN_1>; + linux,code = <KEY_SLEEP>; debounce-interval = <30>; }; @@ -1968,22 +1968,22 @@ }; cooling-maps { - cpu-critical { + map-critical { cooling-device = <&fan 3 3>; trip = <&cpu_trip_critical>; }; - cpu-hot { + map-hot { cooling-device = <&fan 2 2>; trip = <&cpu_trip_hot>; }; - cpu-active { + map-active { cooling-device = <&fan 1 1>; trip = <&cpu_trip_active>; }; - cpu-passive { + map-passive { cooling-device = <&fan 0 0>; trip = <&cpu_trip_passive>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 5f5e5370d709..99fefce41476 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -1461,7 +1461,7 @@ assigned-clock-rates = <81600000>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x702d0000 0x702d0000 0x0000e400>; + ranges = <0x702d0000 0x702d0000 0x00010000>; status = "disabled"; tegra_admaif: admaif@702d0000 { @@ -2164,12 +2164,12 @@ }; cooling-maps { - dram-passive { + map-passive { cooling-device = <&emc 0 0>; trip = <&dram_nominal>; }; - dram-active { + map-active { cooling-device = <&emc 1 1>; trip = <&dram_throttle>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi index 420858a8f4a8..9b990d1cef3f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3737-0000+p3701.dtsi @@ -391,7 +391,7 @@ label = "Force Recovery"; gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; - linux,code = <BTN_1>; + linux,code = <KEY_SLEEP>; }; key-power { @@ -402,13 +402,6 @@ wakeup-event-action = <EV_ACT_ASSERTED>; wakeup-source; }; - - key-suspend { - label = "Suspend"; - gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_SLEEP>; - }; }; fan: pwm-fan { diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts index 97cede1fcb70..8c8c71547996 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3740-0002+p3701-0008.dts @@ -93,6 +93,29 @@ }; }; + typec@28 { + compatible = "st,stusb1600"; + reg = <0x28>; + interrupt-parent = <&gpio>; + interrupts = <TEGRA234_MAIN_GPIO(K, 6) IRQ_TYPE_LEVEL_LOW>; + vdd-supply = <&vdd_5v_sys>; + vsys-supply = <&vdd_3v3_sys>; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + typec-power-opmode = "default"; + + port { + typec_con_ep: endpoint { + remote-endpoint = <&usb_role_switch0>; + }; + }; + }; + }; + /* carrier board ID EEPROM */ eeprom@55 { compatible = "atmel,24c02"; @@ -173,6 +196,12 @@ mode = "otg"; usb-role-switch; status = "okay"; + + port { + usb_role_switch0: endpoint { + remote-endpoint = <&typec_con_ep>; + }; + }; }; usb2-1 { @@ -337,7 +366,7 @@ label = "Force Recovery"; gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; - linux,code = <BTN_1>; + linux,code = <KEY_SLEEP>; }; key-power { @@ -348,13 +377,6 @@ wakeup-event-action = <EV_ACT_ASSERTED>; wakeup-source; }; - - key-suspend { - label = "Suspend"; - gpios = <&gpio TEGRA234_MAIN_GPIO(G, 2) GPIO_ACTIVE_LOW>; - linux,input-type = <EV_KEY>; - linux,code = <KEY_SLEEP>; - }; }; serial { @@ -473,4 +495,11 @@ regulator-boot-on; enable-active-high; }; + + vdd_5v_sys: regulator-vdd-5v-sys { + compatible = "regulator-fixed"; + regulator-name = "vdd-5v-sys"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi index 41821354bbda..9b93074e5aed 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234-p3768-0000+p3767.dtsi @@ -216,7 +216,7 @@ label = "Force Recovery"; gpios = <&gpio TEGRA234_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; linux,input-type = <EV_KEY>; - linux,code = <BTN_1>; + linux,code = <KEY_SLEEP>; }; key-power { diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 5e29316a4d75..5311245334de 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -245,14 +245,14 @@ assigned-clock-rates = <81600000>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x02900000 0x0 0x02900000 0x20000>; tegra_i2s1: i2s@2901000 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901000 0x0 0x100>; + reg = <0x2901000 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S1>, <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -288,7 +288,7 @@ tegra_i2s2: i2s@2901100 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901100 0x0 0x100>; + reg = <0x2901100 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S2>, <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -324,7 +324,7 @@ tegra_i2s3: i2s@2901200 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901200 0x0 0x100>; + reg = <0x2901200 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S3>, <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -360,7 +360,7 @@ tegra_i2s4: i2s@2901300 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901300 0x0 0x100>; + reg = <0x2901300 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S4>, <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -396,7 +396,7 @@ tegra_i2s5: i2s@2901400 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901400 0x0 0x100>; + reg = <0x2901400 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S5>, <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -432,7 +432,7 @@ tegra_i2s6: i2s@2901500 { compatible = "nvidia,tegra234-i2s", "nvidia,tegra210-i2s"; - reg = <0x0 0x2901500 0x0 0x100>; + reg = <0x2901500 0x100>; clocks = <&bpmp TEGRA234_CLK_I2S6>, <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>; clock-names = "i2s", "sync_input"; @@ -468,7 +468,7 @@ tegra_sfc1: sfc@2902000 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902000 0x0 0x200>; + reg = <0x2902000 0x200>; sound-name-prefix = "SFC1"; ports { @@ -496,7 +496,7 @@ tegra_sfc2: sfc@2902200 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902200 0x0 0x200>; + reg = <0x2902200 0x200>; sound-name-prefix = "SFC2"; ports { @@ -524,7 +524,7 @@ tegra_sfc3: sfc@2902400 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902400 0x0 0x200>; + reg = <0x2902400 0x200>; sound-name-prefix = "SFC3"; ports { @@ -552,7 +552,7 @@ tegra_sfc4: sfc@2902600 { compatible = "nvidia,tegra234-sfc", "nvidia,tegra210-sfc"; - reg = <0x0 0x2902600 0x0 0x200>; + reg = <0x2902600 0x200>; sound-name-prefix = "SFC4"; ports { @@ -580,7 +580,7 @@ tegra_amx1: amx@2903000 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x0 0x2903000 0x0 0x100>; + reg = <0x2903000 0x100>; sound-name-prefix = "AMX1"; ports { @@ -632,7 +632,7 @@ tegra_amx2: amx@2903100 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x0 0x2903100 0x0 0x100>; + reg = <0x2903100 0x100>; sound-name-prefix = "AMX2"; ports { @@ -684,7 +684,7 @@ tegra_amx3: amx@2903200 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x0 0x2903200 0x0 0x100>; + reg = <0x2903200 0x100>; sound-name-prefix = "AMX3"; ports { @@ -736,7 +736,7 @@ tegra_amx4: amx@2903300 { compatible = "nvidia,tegra234-amx", "nvidia,tegra194-amx"; - reg = <0x0 0x2903300 0x0 0x100>; + reg = <0x2903300 0x100>; sound-name-prefix = "AMX4"; ports { @@ -788,7 +788,7 @@ tegra_adx1: adx@2903800 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903800 0x0 0x100>; + reg = <0x2903800 0x100>; sound-name-prefix = "ADX1"; ports { @@ -840,7 +840,7 @@ tegra_adx2: adx@2903900 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903900 0x0 0x100>; + reg = <0x2903900 0x100>; sound-name-prefix = "ADX2"; ports { @@ -892,7 +892,7 @@ tegra_adx3: adx@2903a00 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903a00 0x0 0x100>; + reg = <0x2903a00 0x100>; sound-name-prefix = "ADX3"; ports { @@ -944,7 +944,7 @@ tegra_adx4: adx@2903b00 { compatible = "nvidia,tegra234-adx", "nvidia,tegra210-adx"; - reg = <0x0 0x2903b00 0x0 0x100>; + reg = <0x2903b00 0x100>; sound-name-prefix = "ADX4"; ports { @@ -997,7 +997,7 @@ tegra_dmic1: dmic@2904000 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x0 0x2904000 0x0 0x100>; + reg = <0x2904000 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC1>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>; @@ -1031,7 +1031,7 @@ tegra_dmic2: dmic@2904100 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x0 0x2904100 0x0 0x100>; + reg = <0x2904100 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC2>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>; @@ -1065,7 +1065,7 @@ tegra_dmic3: dmic@2904200 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x0 0x2904200 0x0 0x100>; + reg = <0x2904200 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC3>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>; @@ -1099,7 +1099,7 @@ tegra_dmic4: dmic@2904300 { compatible = "nvidia,tegra234-dmic", "nvidia,tegra210-dmic"; - reg = <0x0 0x2904300 0x0 0x100>; + reg = <0x2904300 0x100>; clocks = <&bpmp TEGRA234_CLK_DMIC4>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>; @@ -1133,7 +1133,7 @@ tegra_dspk1: dspk@2905000 { compatible = "nvidia,tegra234-dspk", "nvidia,tegra186-dspk"; - reg = <0x0 0x2905000 0x0 0x100>; + reg = <0x2905000 0x100>; clocks = <&bpmp TEGRA234_CLK_DSPK1>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>; @@ -1167,7 +1167,7 @@ tegra_dspk2: dspk@2905100 { compatible = "nvidia,tegra234-dspk", "nvidia,tegra186-dspk"; - reg = <0x0 0x2905100 0x0 0x100>; + reg = <0x2905100 0x100>; clocks = <&bpmp TEGRA234_CLK_DSPK2>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>; @@ -1201,23 +1201,23 @@ tegra_ope1: processing-engine@2908000 { compatible = "nvidia,tegra234-ope", "nvidia,tegra210-ope"; - reg = <0x0 0x2908000 0x0 0x100>; + reg = <0x2908000 0x100>; sound-name-prefix = "OPE1"; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; ranges; equalizer@2908100 { compatible = "nvidia,tegra234-peq", "nvidia,tegra210-peq"; - reg = <0x0 0x2908100 0x0 0x100>; + reg = <0x2908100 0x100>; }; dynamic-range-compressor@2908200 { compatible = "nvidia,tegra234-mbdrc", "nvidia,tegra210-mbdrc"; - reg = <0x0 0x2908200 0x0 0x200>; + reg = <0x2908200 0x200>; }; ports { @@ -1247,7 +1247,7 @@ tegra_mvc1: mvc@290a000 { compatible = "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; - reg = <0x0 0x290a000 0x0 0x200>; + reg = <0x290a000 0x200>; sound-name-prefix = "MVC1"; ports { @@ -1275,7 +1275,7 @@ tegra_mvc2: mvc@290a200 { compatible = "nvidia,tegra234-mvc", "nvidia,tegra210-mvc"; - reg = <0x0 0x290a200 0x0 0x200>; + reg = <0x290a200 0x200>; sound-name-prefix = "MVC2"; ports { @@ -1303,7 +1303,7 @@ tegra_amixer: amixer@290bb00 { compatible = "nvidia,tegra234-amixer", "nvidia,tegra210-amixer"; - reg = <0x0 0x290bb00 0x0 0x800>; + reg = <0x290bb00 0x800>; sound-name-prefix = "MIXER1"; ports { @@ -1435,7 +1435,7 @@ tegra_admaif: admaif@290f000 { compatible = "nvidia,tegra234-admaif", "nvidia,tegra186-admaif"; - reg = <0x0 0x0290f000 0x0 0x1000>; + reg = <0x0290f000 0x1000>; dmas = <&adma 1>, <&adma 1>, <&adma 2>, <&adma 2>, <&adma 3>, <&adma 3>, @@ -1650,7 +1650,7 @@ tegra_asrc: asrc@2910000 { compatible = "nvidia,tegra234-asrc", "nvidia,tegra186-asrc"; - reg = <0x0 0x2910000 0x0 0x2000>; + reg = <0x2910000 0x2000>; sound-name-prefix = "ASRC1"; ports { diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi index 58cd81bc33d7..f39f33a66cd2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi @@ -38,5 +38,62 @@ cmdqv@6200000 { status = "okay"; }; + + i2c@c640000 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + label = "module"; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + }; + + bpmp { + i2c { + status = "okay"; + + thermal-sensor@4c { + compatible = "ti,tmp451"; + reg = <0x4c>; + }; + }; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <40>; + polling-delay = <1000>; + status = "okay"; + }; + + gpu-thermal { + polling-delay-passive = <40>; + polling-delay = <1000>; + status = "okay"; + }; + + soc012-thermal { + polling-delay-passive = <40>; + polling-delay = <1000>; + status = "okay"; + }; + + soc345-thermal { + polling-delay-passive = <40>; + polling-delay = <1000>; + status = "okay"; + }; + + tj-thermal { + polling-delay-passive = <40>; + polling-delay = <1000>; + status = "okay"; + }; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi index 4550e843f513..9295f9c81296 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/input/gpio-keys.h> + / { aliases { serial0 = &{/bus@0/serial@c4e0000}; @@ -11,15 +14,105 @@ }; bus@0 { + rtc@c2c0000 { + status = "okay"; + }; + pwm@c6a0000 { status = "okay"; }; }; + bus@8100000000 { + i2c@c640000 { + eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + label = "system"; + address-width = <8>; + pagesize = <8>; + size = <256>; + read-only; + }; + }; + }; + fan: pwm-fan { compatible = "pwm-fan"; cooling-levels = <77 102 140 192 255>; pwms = <&pwm4 0 40000>; #cooling-cells = <2>; }; + + gpio-keys { + compatible = "gpio-keys"; + + key-force-recovery { + label = "Force Recovery"; + gpios = <&gpio_aon TEGRA264_AON_GPIO(EE, 1) GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_SLEEP>; + }; + + key-power { + label = "Power"; + gpios = <&gpio_aon TEGRA264_AON_GPIO(AA, 5) GPIO_ACTIVE_LOW>; + linux,input-type = <EV_KEY>; + linux,code = <KEY_POWER>; + wakeup-event-action = <EV_ACT_ASSERTED>; + wakeup-source; + }; + }; + + thermal-zones { + tj-thermal { + trips { + tj_trip_active0: active-0 { + temperature = <80000>; + hysteresis = <0>; + type = "active"; + }; + + tj_trip_active1: active-1 { + temperature = <86000>; + hysteresis = <0>; + type = "active"; + }; + + tj_trip_active2: active-2 { + temperature = <91000>; + hysteresis = <0>; + type = "active"; + }; + + tj_trip_active3: active-3 { + temperature = <100000>; + hysteresis = <0>; + type = "active"; + }; + }; + + cooling-maps { + map-active-0 { + cooling-device = <&fan 0 1>; + trip = <&tj_trip_active0>; + }; + + map-active-1 { + cooling-device = <&fan 1 2>; + trip = <&tj_trip_active1>; + }; + + map-active-2 { + cooling-device = <&fan 2 3>; + trip = <&tj_trip_active2>; + }; + + map-active-3 { + cooling-device = <&fan 3 4>; + trip = <&tj_trip_active3>; + }; + }; + }; + }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi index 6b2e3a6ab810..c04d0e5df85b 100644 --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi @@ -1,18 +1,40 @@ // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause #include <dt-bindings/clock/nvidia,tegra264.h> +#include <dt-bindings/gpio/nvidia,tegra264-gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/tegra186-hsp.h> #include <dt-bindings/memory/nvidia,tegra264.h> #include <dt-bindings/power/nvidia,tegra264-bpmp.h> #include <dt-bindings/reset/nvidia,tegra264.h> +#include "thermal/nvidia,tegra264-bpmp.h" + / { compatible = "nvidia,tegra264"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &{/bpmp/i2c}; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c14 = &i2c14; + i2c15 = &i2c15; + i2c16 = &i2c16; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -40,6 +62,13 @@ <0x0 0x0c140000 0x0 0x10000>; }; + fuse@1000000 { + compatible = "nvidia,tegra264-efuse"; + reg = <0x0 0x1000000 0x0 0x20000>; + clocks = <&bpmp TEGRA264_CLK_FUSE>; + clock-names = "fuse"; + }; + timer@8000000 { compatible = "nvidia,tegra234-timer"; reg = <0x0 0x08000000 0x0 0x140000>; @@ -122,85 +151,85 @@ aconnect@9000000 { compatible = "nvidia,tegra264-aconnect", - "nvidia,tegra210-aconnect"; + "nvidia,tegra210-aconnect"; clocks = <&bpmp TEGRA264_CLK_APE>, - <&bpmp TEGRA264_CLK_ADSP>; + <&bpmp TEGRA264_CLK_ADSP>; clock-names = "ape", "apb2ape"; power-domains = <&bpmp TEGRA264_POWER_DOMAIN_AUD>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x9000000 0x0 0x9000000 0x0 0x2000000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x9000000 0x0 0x9000000 0x2000000>; adma: dma-controller@9440000 { compatible = "nvidia,tegra264-adma"; - reg = <0x0 0x9440000 0x0 0xb0000>; + reg = <0x9440000 0xb0000>; interrupt-parent = <&agic_page0>; interrupts = <GIC_SPI 0x90 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x92 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x93 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x94 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x95 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x96 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x97 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x98 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x99 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x9a IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x9b IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x9c IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x9d IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x9e IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0x9f IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xa0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xa1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xa2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xa3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xa4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xa5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xa6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xa7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xa8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xa9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xaa IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xab IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xac IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xad IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xae IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xaf IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xb0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xb1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xb2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xb3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xb4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xb5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xb6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xb7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xb8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xb9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xba IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xbb IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xbc IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xbd IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xbe IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xbf IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xc0 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xc1 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xc2 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xc3 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xc4 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xc5 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xc6 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xc7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xc8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xc9 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xca IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xcb IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xcc IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xcd IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xce IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 0xcf IRQ_TYPE_LEVEL_HIGH>; + <GIC_SPI 0x91 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x92 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x94 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x95 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x9a IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x9b IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x9c IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x9d IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x9e IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0x9f IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xa0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xa1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xa2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xa3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xa4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xa5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xa6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xa7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xa8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xa9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xaa IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xab IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xac IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xad IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xae IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xaf IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xb0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xb1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xb2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xb3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xb4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xb5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xb6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xb7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xb8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xb9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xba IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xbb IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xbc IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xbd IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xbe IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xbf IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xc0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xc1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xc2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xc3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xc4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xc5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xc6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xc7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xc8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xc9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xca IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xcb IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xcc IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xcd IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xce IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0xcf IRQ_TYPE_LEVEL_HIGH>; #dma-cells = <1>; clocks = <&bpmp TEGRA264_CLK_AHUB>; clock-names = "d_audio"; @@ -209,24 +238,24 @@ tegra_ahub: ahub@9630000 { compatible = "nvidia,tegra264-ahub"; - reg = <0x0 0x9630000 0x0 0x10000>; + reg = <0x9630000 0x10000>; clocks = <&bpmp TEGRA264_CLK_AHUB>; clock-names = "ahub"; assigned-clocks = <&bpmp TEGRA264_CLK_AHUB>; assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLAON_APE>; status = "disabled"; - #address-cells = <2>; - #size-cells = <2>; + #address-cells = <1>; + #size-cells = <1>; /* ADMA is under AHUB range, its excluded in the defined range */ - ranges = <0x0 0x9280000 0x0 0x9280000 0x0 0x1c0000>, - <0x0 0x9510000 0x0 0x9510000 0x0 0x370000>; + ranges = <0x9280000 0x9280000 0x1c0000>, + <0x9510000 0x9510000 0x370000>; tegra_i2s1: i2s@9280000 { compatible = "nvidia,tegra264-i2s"; - reg = <0x0 0x9280000 0x0 0x10000>; + reg = <0x9280000 0x10000>; clocks = <&bpmp TEGRA264_CLK_I2S1>, - <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S1_SCLK_IN>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA264_CLK_I2S1>; assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -259,7 +288,7 @@ tegra_i2s2: i2s@9290000 { compatible = "nvidia,tegra264-i2s"; - reg = <0x0 0x9290000 0x0 0x10000>; + reg = <0x9290000 0x10000>; clocks = <&bpmp TEGRA264_CLK_I2S2>, <&bpmp TEGRA264_CLK_I2S2_SCLK_IN>; clock-names = "i2s", "sync_input"; @@ -294,9 +323,9 @@ tegra_i2s3: i2s@92a0000 { compatible = "nvidia,tegra264-i2s"; - reg = <0x0 0x92a0000 0x0 0x10000>; + reg = <0x92a0000 0x10000>; clocks = <&bpmp TEGRA264_CLK_I2S3>, - <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S3_SCLK_IN>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA264_CLK_I2S3>; assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -329,9 +358,9 @@ tegra_i2s4: i2s@92b0000 { compatible = "nvidia,tegra264-i2s"; - reg = <0x0 0x92b0000 0x0 0x10000>; + reg = <0x92b0000 0x10000>; clocks = <&bpmp TEGRA264_CLK_I2S4>, - <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S4_SCLK_IN>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA264_CLK_I2S4>; assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -364,9 +393,9 @@ tegra_i2s5: i2s@92c0000 { compatible = "nvidia,tegra264-i2s"; - reg = <0x0 0x92c0000 0x0 0x10000>; + reg = <0x92c0000 0x10000>; clocks = <&bpmp TEGRA264_CLK_I2S5>, - <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S5_SCLK_IN>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA264_CLK_I2S5>; assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -399,9 +428,9 @@ tegra_i2s6: i2s@92d0000 { compatible = "nvidia,tegra264-i2s"; - reg = <0x0 0x92d0000 0x0 0x10000>; + reg = <0x92d0000 0x10000>; clocks = <&bpmp TEGRA264_CLK_I2S6>, - <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S6_SCLK_IN>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA264_CLK_I2S6>; assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -434,9 +463,9 @@ tegra_i2s7: i2s@92e0000 { compatible = "nvidia,tegra264-i2s"; - reg = <0x0 0x92e0000 0x0 0x10000>; + reg = <0x92e0000 0x10000>; clocks = <&bpmp TEGRA264_CLK_I2S7>, - <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S7_SCLK_IN>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA264_CLK_I2S7>; assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -469,9 +498,9 @@ tegra_i2s8: i2s@92f0000 { compatible = "nvidia,tegra264-i2s"; - reg = <0x0 0x92f0000 0x0 0x10000>; + reg = <0x92f0000 0x10000>; clocks = <&bpmp TEGRA264_CLK_I2S8>, - <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>; + <&bpmp TEGRA264_CLK_I2S8_SCLK_IN>; clock-names = "i2s", "sync_input"; assigned-clocks = <&bpmp TEGRA264_CLK_I2S8>; assigned-clock-parents = <&bpmp TEGRA264_CLK_PLLA1_OUT1>; @@ -504,8 +533,8 @@ tegra_dmic1: dmic@9300000 { compatible = "nvidia,tegra264-dmic", - "nvidia,tegra210-dmic"; - reg = <0x0 0x9300000 0x0 0x10000>; + "nvidia,tegra210-dmic"; + reg = <0x9300000 0x10000>; clocks = <&bpmp TEGRA264_CLK_DMIC1>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>; @@ -538,8 +567,8 @@ tegra_dmic2: dmic@9310000 { compatible = "nvidia,tegra264-dmic", - "nvidia,tegra210-dmic"; - reg = <0x0 0x9310000 0x0 0x10000>; + "nvidia,tegra210-dmic"; + reg = <0x9310000 0x10000>; clocks = <&bpmp TEGRA264_CLK_DMIC1>; clock-names = "dmic"; assigned-clocks = <&bpmp TEGRA264_CLK_DMIC1>; @@ -572,8 +601,8 @@ tegra_dspk1: dspk@9380000 { compatible = "nvidia,tegra264-dspk", - "nvidia,tegra186-dspk"; - reg = <0x0 0x9380000 0x0 0x10000>; + "nvidia,tegra186-dspk"; + reg = <0x9380000 0x10000>; clocks = <&bpmp TEGRA264_CLK_DSPK1>; clock-names = "dspk"; assigned-clocks = <&bpmp TEGRA264_CLK_DSPK1>; @@ -606,7 +635,7 @@ tegra_amx1: amx@9510000 { compatible = "nvidia,tegra264-amx"; - reg = <0x0 0x9510000 0x0 0x10000>; + reg = <0x9510000 0x10000>; sound-name-prefix = "AMX1"; ports { @@ -657,7 +686,7 @@ tegra_amx2: amx@9520000 { compatible = "nvidia,tegra264-amx"; - reg = <0x0 0x9520000 0x0 0x10000>; + reg = <0x9520000 0x10000>; sound-name-prefix = "AMX2"; ports { @@ -708,7 +737,7 @@ tegra_amx3: amx@9530000 { compatible = "nvidia,tegra264-amx"; - reg = <0x0 0x9530000 0x0 0x10000>; + reg = <0x9530000 0x10000>; sound-name-prefix = "AMX3"; ports { @@ -759,7 +788,7 @@ tegra_amx4: amx@9540000 { compatible = "nvidia,tegra264-amx"; - reg = <0x0 0x9540000 0x0 0x10000>; + reg = <0x9540000 0x10000>; sound-name-prefix = "AMX4"; ports { @@ -810,7 +839,7 @@ tegra_amx5: amx@9550000 { compatible = "nvidia,tegra264-amx"; - reg = <0x0 0x9550000 0x0 0x10000>; + reg = <0x9550000 0x10000>; sound-name-prefix = "AMX5"; ports { @@ -861,7 +890,7 @@ tegra_amx6: amx@9560000 { compatible = "nvidia,tegra264-amx"; - reg = <0x0 0x9560000 0x0 0x10000>; + reg = <0x9560000 0x10000>; sound-name-prefix = "AMX6"; ports { @@ -912,7 +941,7 @@ tegra_adx1: adx@9590000 { compatible = "nvidia,tegra264-adx"; - reg = <0x0 0x9590000 0x0 0x10000>; + reg = <0x9590000 0x10000>; sound-name-prefix = "ADX1"; ports { @@ -963,7 +992,7 @@ tegra_adx2: adx@95a0000 { compatible = "nvidia,tegra264-adx"; - reg = <0x0 0x95a0000 0x0 0x10000>; + reg = <0x95a0000 0x10000>; sound-name-prefix = "ADX2"; ports { @@ -1014,7 +1043,7 @@ tegra_adx3: adx@95b0000 { compatible = "nvidia,tegra264-adx"; - reg = <0x0 0x95b0000 0x0 0x10000>; + reg = <0x95b0000 0x10000>; sound-name-prefix = "ADX3"; ports { @@ -1065,7 +1094,7 @@ tegra_adx4: adx@95c0000 { compatible = "nvidia,tegra264-adx"; - reg = <0x0 0x95c0000 0x0 0x10000>; + reg = <0x95c0000 0x10000>; sound-name-prefix = "ADX4"; ports { @@ -1116,7 +1145,7 @@ tegra_adx5: adx@95d0000 { compatible = "nvidia,tegra264-adx"; - reg = <0x0 0x95d0000 0x0 0x10000>; + reg = <0x95d0000 0x10000>; sound-name-prefix = "ADX5"; ports { @@ -1167,7 +1196,7 @@ tegra_adx6: adx@95e0000 { compatible = "nvidia,tegra264-adx"; - reg = <0x0 0x95e0000 0x0 0x10000>; + reg = <0x95e0000 0x10000>; sound-name-prefix = "ADX6"; ports { @@ -1218,76 +1247,75 @@ tegra_admaif: admaif@9610000 { compatible = "nvidia,tegra264-admaif"; - reg = <0x0 0x9610000 0x0 0x10000>; + reg = <0x9610000 0x10000>; dmas = <&adma 1>, <&adma 1>, - <&adma 2>, <&adma 2>, - <&adma 3>, <&adma 3>, - <&adma 4>, <&adma 4>, - <&adma 5>, <&adma 5>, - <&adma 6>, <&adma 6>, - <&adma 7>, <&adma 7>, - <&adma 8>, <&adma 8>, - <&adma 9>, <&adma 9>, - <&adma 10>, <&adma 10>, - <&adma 11>, <&adma 11>, - <&adma 12>, <&adma 12>, - <&adma 13>, <&adma 13>, - <&adma 14>, <&adma 14>, - <&adma 15>, <&adma 15>, - <&adma 16>, <&adma 16>, - <&adma 17>, <&adma 17>, - <&adma 18>, <&adma 18>, - <&adma 19>, <&adma 19>, - <&adma 20>, <&adma 20>, - <&adma 21>, <&adma 21>, - <&adma 22>, <&adma 22>, - <&adma 23>, <&adma 23>, - <&adma 24>, <&adma 24>, - <&adma 25>, <&adma 25>, - <&adma 26>, <&adma 26>, - <&adma 27>, <&adma 27>, - <&adma 28>, <&adma 28>, - <&adma 29>, <&adma 29>, - <&adma 30>, <&adma 30>, - <&adma 31>, <&adma 31>, - <&adma 32>, <&adma 32>; + <&adma 2>, <&adma 2>, + <&adma 3>, <&adma 3>, + <&adma 4>, <&adma 4>, + <&adma 5>, <&adma 5>, + <&adma 6>, <&adma 6>, + <&adma 7>, <&adma 7>, + <&adma 8>, <&adma 8>, + <&adma 9>, <&adma 9>, + <&adma 10>, <&adma 10>, + <&adma 11>, <&adma 11>, + <&adma 12>, <&adma 12>, + <&adma 13>, <&adma 13>, + <&adma 14>, <&adma 14>, + <&adma 15>, <&adma 15>, + <&adma 16>, <&adma 16>, + <&adma 17>, <&adma 17>, + <&adma 18>, <&adma 18>, + <&adma 19>, <&adma 19>, + <&adma 20>, <&adma 20>, + <&adma 21>, <&adma 21>, + <&adma 22>, <&adma 22>, + <&adma 23>, <&adma 23>, + <&adma 24>, <&adma 24>, + <&adma 25>, <&adma 25>, + <&adma 26>, <&adma 26>, + <&adma 27>, <&adma 27>, + <&adma 28>, <&adma 28>, + <&adma 29>, <&adma 29>, + <&adma 30>, <&adma 30>, + <&adma 31>, <&adma 31>, + <&adma 32>, <&adma 32>; dma-names = "rx1", "tx1", - "rx2", "tx2", - "rx3", "tx3", - "rx4", "tx4", - "rx5", "tx5", - "rx6", "tx6", - "rx7", "tx7", - "rx8", "tx8", - "rx9", "tx9", - "rx10", "tx10", - "rx11", "tx11", - "rx12", "tx12", - "rx13", "tx13", - "rx14", "tx14", - "rx15", "tx15", - "rx16", "tx16", - "rx17", "tx17", - "rx18", "tx18", - "rx19", "tx19", - "rx20", "tx20", - "rx21", "tx21", - "rx22", "tx22", - "rx23", "tx23", - "rx24", "tx24", - "rx25", "tx25", - "rx26", "tx26", - "rx27", "tx27", - "rx28", "tx28", - "rx29", "tx29", - "rx30", "tx30", - "rx31", "tx31", - "rx32", "tx32"; - - interconnects = - <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>, - <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>; - interconnect-names = "dma-mem", "write"; + "rx2", "tx2", + "rx3", "tx3", + "rx4", "tx4", + "rx5", "tx5", + "rx6", "tx6", + "rx7", "tx7", + "rx8", "tx8", + "rx9", "tx9", + "rx10", "tx10", + "rx11", "tx11", + "rx12", "tx12", + "rx13", "tx13", + "rx14", "tx14", + "rx15", "tx15", + "rx16", "tx16", + "rx17", "tx17", + "rx18", "tx18", + "rx19", "tx19", + "rx20", "tx20", + "rx21", "tx21", + "rx22", "tx22", + "rx23", "tx23", + "rx24", "tx24", + "rx25", "tx25", + "rx26", "tx26", + "rx27", "tx27", + "rx28", "tx28", + "rx29", "tx29", + "rx30", "tx30", + "rx31", "tx31", + "rx32", "tx32"; + + interconnects = <&mc TEGRA264_MEMORY_CLIENT_APEDMAR &emc>, + <&mc TEGRA264_MEMORY_CLIENT_APEDMAW &emc>; + interconnect-names = "dma-mem", "write"; iommus = <&smmu1 TEGRA264_SID_APE>; @@ -1555,8 +1583,8 @@ tegra_sfc1: sfc@9700000 { compatible = "nvidia,tegra264-sfc", - "nvidia,tegra210-sfc"; - reg = <0x0 0x9700000 0x0 0x10000>; + "nvidia,tegra210-sfc"; + reg = <0x9700000 0x10000>; sound-name-prefix = "SFC1"; ports { @@ -1583,8 +1611,8 @@ tegra_sfc2: sfc@9710000 { compatible = "nvidia,tegra264-sfc", - "nvidia,tegra210-sfc"; - reg = <0x0 0x9710000 0x0 0x10000>; + "nvidia,tegra210-sfc"; + reg = <0x9710000 0x10000>; sound-name-prefix = "SFC2"; ports { @@ -1611,8 +1639,8 @@ tegra_sfc3: sfc@9720000 { compatible = "nvidia,tegra264-sfc", - "nvidia,tegra210-sfc"; - reg = <0x0 0x9720000 0x0 0x10000>; + "nvidia,tegra210-sfc"; + reg = <0x9720000 0x10000>; sound-name-prefix = "SFC3"; ports { @@ -1639,8 +1667,8 @@ tegra_sfc4: sfc@9730000 { compatible = "nvidia,tegra264-sfc", - "nvidia,tegra210-sfc"; - reg = <0x0 0x9730000 0x0 0x10000>; + "nvidia,tegra210-sfc"; + reg = <0x9730000 0x10000>; sound-name-prefix = "SFC4"; ports { @@ -1667,23 +1695,23 @@ tegra_ope1: processing-engine@9780000 { compatible = "nvidia,tegra264-ope", - "nvidia,tegra210-ope"; - reg = <0x0 0x9780000 0x0 0x10000>; - #address-cells = <2>; - #size-cells = <2>; - ranges = <0x0 0x9780000 0x0 0x9780000 0x0 0x30000>; + "nvidia,tegra210-ope"; + reg = <0x9780000 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x9780000 0x9780000 0x30000>; sound-name-prefix = "OPE1"; equalizer@9790000 { compatible = "nvidia,tegra264-peq", - "nvidia,tegra210-peq"; - reg = <0x0 0x9790000 0x0 0x10000>; + "nvidia,tegra210-peq"; + reg = <0x9790000 0x10000>; }; dynamic-range-compressor@97a0000 { compatible = "nvidia,tegra264-mbdrc", - "nvidia,tegra210-mbdrc"; - reg = <0x0 0x97a0000 0x0 0x10000>; + "nvidia,tegra210-mbdrc"; + reg = <0x97a0000 0x10000>; }; ports { @@ -1694,8 +1722,7 @@ reg = <0x0>; ope1_cif_in_ep: endpoint { - remote-endpoint = - <&xbar_ope1_in_ep>; + remote-endpoint = <&xbar_ope1_in_ep>; }; }; @@ -1703,8 +1730,7 @@ reg = <0x1>; ope1_cif_out_ep: endpoint { - remote-endpoint = - <&xbar_ope1_out_ep>; + remote-endpoint = <&xbar_ope1_out_ep>; }; }; }; @@ -1712,8 +1738,8 @@ tegra_mvc1: mvc@9800000 { compatible = "nvidia,tegra264-mvc", - "nvidia,tegra210-mvc"; - reg = <0x0 0x9800000 0x0 0x10000>; + "nvidia,tegra210-mvc"; + reg = <0x9800000 0x10000>; sound-name-prefix = "MVC1"; ports { @@ -1740,8 +1766,8 @@ tegra_mvc2: mvc@9810000 { compatible = "nvidia,tegra264-mvc", - "nvidia,tegra210-mvc"; - reg = <0x0 0x9810000 0x0 0x10000>; + "nvidia,tegra210-mvc"; + reg = <0x9810000 0x10000>; sound-name-prefix = "MVC2"; ports { @@ -1768,8 +1794,8 @@ tegra_amixer: amixer@9820000 { compatible = "nvidia,tegra264-amixer", - "nvidia,tegra210-amixer"; - reg = <0x0 0x9820000 0x0 0x10000>; + "nvidia,tegra210-amixer"; + reg = <0x9820000 0x10000>; sound-name-prefix = "MIXER1"; ports { @@ -1900,7 +1926,7 @@ tegra_asrc: asrc@9850000 { compatible = "nvidia,tegra264-asrc"; - reg = <0x0 0x9850000 0x0 0x10000>; + reg = <0x9850000 0x10000>; sound-name-prefix = "ASRC1"; ports { @@ -1911,8 +1937,7 @@ reg = <0x0>; asrc_in1_ep: endpoint { - remote-endpoint = - <&xbar_asrc_in1_ep>; + remote-endpoint = <&xbar_asrc_in1_ep>; }; }; @@ -1920,8 +1945,7 @@ reg = <0x1>; asrc_in2_ep: endpoint { - remote-endpoint = - <&xbar_asrc_in2_ep>; + remote-endpoint = <&xbar_asrc_in2_ep>; }; }; @@ -1929,8 +1953,7 @@ reg = <0x2>; asrc_in3_ep: endpoint { - remote-endpoint = - <&xbar_asrc_in3_ep>; + remote-endpoint = <&xbar_asrc_in3_ep>; }; }; @@ -1938,8 +1961,7 @@ reg = <0x3>; asrc_in4_ep: endpoint { - remote-endpoint = - <&xbar_asrc_in4_ep>; + remote-endpoint = <&xbar_asrc_in4_ep>; }; }; @@ -1947,8 +1969,7 @@ reg = <0x4>; asrc_in5_ep: endpoint { - remote-endpoint = - <&xbar_asrc_in5_ep>; + remote-endpoint = <&xbar_asrc_in5_ep>; }; }; @@ -1956,8 +1977,7 @@ reg = <0x5>; asrc_in6_ep: endpoint { - remote-endpoint = - <&xbar_asrc_in6_ep>; + remote-endpoint = <&xbar_asrc_in6_ep>; }; }; @@ -1965,8 +1985,7 @@ reg = <0x6>; asrc_in7_ep: endpoint { - remote-endpoint = - <&xbar_asrc_in7_ep>; + remote-endpoint = <&xbar_asrc_in7_ep>; }; }; @@ -1974,8 +1993,7 @@ reg = <0x7>; asrc_out1_ep: endpoint { - remote-endpoint = - <&xbar_asrc_out1_ep>; + remote-endpoint = <&xbar_asrc_out1_ep>; }; }; @@ -1983,8 +2001,7 @@ reg = <0x8>; asrc_out2_ep: endpoint { - remote-endpoint = - <&xbar_asrc_out2_ep>; + remote-endpoint = <&xbar_asrc_out2_ep>; }; }; @@ -1992,8 +2009,7 @@ reg = <0x9>; asrc_out3_ep: endpoint { - remote-endpoint = - <&xbar_asrc_out3_ep>; + remote-endpoint = <&xbar_asrc_out3_ep>; }; }; @@ -2001,8 +2017,7 @@ reg = <0xa>; asrc_out4_ep: endpoint { - remote-endpoint = - <&xbar_asrc_out4_ep>; + remote-endpoint = <&xbar_asrc_out4_ep>; }; }; @@ -2010,8 +2025,7 @@ reg = <0xb>; asrc_out5_ep: endpoint { - remote-endpoint = - <&xbar_asrc_out5_ep>; + remote-endpoint = <&xbar_asrc_out5_ep>; }; }; @@ -2019,8 +2033,7 @@ reg = <0xc>; asrc_out6_ep: endpoint { - remote-endpoint = - <&xbar_asrc_out6_ep>; + remote-endpoint = <&xbar_asrc_out6_ep>; }; }; }; @@ -3194,13 +3207,12 @@ agic_page0: interrupt-controller@9960000 { compatible = "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x0 0x9961000 0x0 0x1000>, - <0x0 0x9962000 0x0 0x1000>; - interrupts = <GIC_SPI 0x230 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x9961000 0x1000>, + <0x9962000 0x1000>; + interrupts = <GIC_SPI 0x230 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&bpmp TEGRA264_CLK_ADSP>; clock-names = "clk"; status = "disabled"; @@ -3208,13 +3220,12 @@ agic_page1: interrupt-controller@9970000 { compatible = "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x0 0x9971000 0x0 0x1000>, - <0x0 0x9972000 0x0 0x1000>; - interrupts = <GIC_SPI 0x231 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x9971000 0x1000>, + <0x9972000 0x1000>; + interrupts = <GIC_SPI 0x231 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&bpmp TEGRA264_CLK_ADSP>; clock-names = "clk"; status = "disabled"; @@ -3222,13 +3233,12 @@ agic_page2: interrupt-controller@9980000 { compatible = "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x0 0x9981000 0x0 0x1000>, - <0x0 0x9982000 0x0 0x1000>; - interrupts = <GIC_SPI 0x232 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x9981000 0x1000>, + <0x9982000 0x1000>; + interrupts = <GIC_SPI 0x232 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&bpmp TEGRA264_CLK_ADSP>; clock-names = "clk"; status = "disabled"; @@ -3236,13 +3246,12 @@ agic_page3: interrupt-controller@9990000 { compatible = "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x0 0x9991000 0x0 0x1000>, - <0x0 0x9992000 0x0 0x1000>; - interrupts = <GIC_SPI 0x233 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x9991000 0x1000>, + <0x9992000 0x1000>; + interrupts = <GIC_SPI 0x233 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&bpmp TEGRA264_CLK_ADSP>; clock-names = "clk"; status = "disabled"; @@ -3250,13 +3259,12 @@ agic_page4: interrupt-controller@99a0000 { compatible = "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x0 0x99a1000 0x0 0x1000>, - <0x0 0x99a2000 0x0 0x1000>; - interrupts = <GIC_SPI 0x234 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x99a1000 0x1000>, + <0x99a2000 0x1000>; + interrupts = <GIC_SPI 0x234 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&bpmp TEGRA264_CLK_ADSP>; clock-names = "clk"; status = "disabled"; @@ -3264,13 +3272,12 @@ agic_page5: interrupt-controller@99b0000 { compatible = "nvidia,tegra264-agic", - "nvidia,tegra210-agic"; + "nvidia,tegra210-agic"; #interrupt-cells = <3>; interrupt-controller; - reg = <0x0 0x99b1000 0x0 0x1000>, - <0x0 0x99b2000 0x0 0x1000>; - interrupts = <GIC_SPI 0x235 - (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + reg = <0x99b1000 0x1000>, + <0x99b2000 0x1000>; + interrupts = <GIC_SPI 0x235 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&bpmp TEGRA264_CLK_ADSP>; clock-names = "clk"; status = "disabled"; @@ -3330,6 +3337,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x0 0x0c600000 0x0 0x10000>; interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_AON_I2C>, <&bpmp TEGRA264_CLK_PLLAON>; @@ -3345,6 +3354,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x0 0x0c610000 0x0 0x10000>; interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_AON_I2C>, <&bpmp TEGRA264_CLK_PLLAON>; @@ -3642,6 +3653,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c410000 0x0 0x10000>; interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3657,6 +3670,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c420000 0x0 0x10000>; interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3672,6 +3687,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c430000 0x0 0x10000>; interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3747,6 +3764,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c630000 0x0 0x10000>; interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3762,6 +3781,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c640000 0x0 0x10000>; interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3777,6 +3798,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c650000 0x0 0x10000>; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3792,6 +3815,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c670000 0x0 0x10000>; interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3807,6 +3832,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c680000 0x0 0x10000>; interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3822,6 +3849,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c690000 0x0 0x10000>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3837,6 +3866,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c6a0000 0x0 0x10000>; interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3852,6 +3883,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c6b0000 0x0 0x10000>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3867,6 +3900,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c6c0000 0x0 0x10000>; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -3882,6 +3917,8 @@ compatible = "nvidia,tegra264-i2c"; reg = <0x00 0x0c6d0000 0x0 0x10000>; interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; clock-frequency = <400000>; clocks = <&bpmp TEGRA264_CLK_TOP_I2C>, <&bpmp TEGRA264_CLK_PLLP_OUT0>; @@ -4685,6 +4722,33 @@ status = "disabled"; }; + thermal-zones { + cpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_CPU_MAX>; + status = "disabled"; + }; + + gpu-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_GPU_MAX>; + status = "disabled"; + }; + + soc012-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_SOC_012_MAX>; + status = "disabled"; + }; + + soc345-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_SOC_345_MAX>; + status = "disabled"; + }; + + tj-thermal { + thermal-sensors = <&{/bpmp/thermal} TEGRA264_THERMAL_ZONE_TJ_MAX>; + status = "disabled"; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, diff --git a/arch/arm64/boot/dts/nvidia/thermal/nvidia,tegra264-bpmp.h b/arch/arm64/boot/dts/nvidia/thermal/nvidia,tegra264-bpmp.h new file mode 100644 index 000000000000..29695881f4cc --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/thermal/nvidia,tegra264-bpmp.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* SPDX-FileCopyrightText: Copyright (c) 2023-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. */ + +#ifndef DT_BINDINGS_THERMAL_NVIDIA_TEGRA264_BPMP_H +#define DT_BINDINGS_THERMAL_NVIDIA_TEGRA264_BPMP_H + +#define TEGRA264_THERMAL_ZONE_TJ_MAX 0 +#define TEGRA264_THERMAL_ZONE_TJ_MIN 1 +#define TEGRA264_THERMAL_ZONE_GPU_AVG 2 +#define TEGRA264_THERMAL_ZONE_CPU_AVG 3 +#define TEGRA264_THERMAL_ZONE_SOC_012_AVG 4 +#define TEGRA264_THERMAL_ZONE_SOC_45_AVG 5 +#define TEGRA264_THERMAL_ZONE_SOC_3_AVG 6 +#define TEGRA264_THERMAL_ZONE_GPU_MAX 7 +#define TEGRA264_THERMAL_ZONE_CPU_MAX 8 +#define TEGRA264_THERMAL_ZONE_SOC_012_MAX 9 +#define TEGRA264_THERMAL_ZONE_SOC_345_MAX 10 +#define TEGRA264_THERMAL_ZONE_TJ_AVG 11 + +#endif /* DT_BINDINGS_THERMAL_NVIDIA_TEGRA264_BPMP_H */ diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index 39654964c35c..b8c8ccf80056 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -65,6 +65,9 @@ static struct tegra_fuse *fuse = &(struct tegra_fuse) { }; static const struct of_device_id tegra_fuse_match[] = { +#ifdef CONFIG_ARCH_TEGRA_264_SOC + { .compatible = "nvidia,tegra264-efuse", .data = &tegra264_fuse_soc }, +#endif #ifdef CONFIG_ARCH_TEGRA_234_SOC { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc }, #endif @@ -176,6 +179,11 @@ static int tegra_fuse_probe(struct platform_device *pdev) fuse->soc = &tegra241_fuse_soc; break; #endif +#if defined(CONFIG_ARCH_TEGRA_264_SOC) + case TEGRA264: + fuse->soc = &tegra264_fuse_soc; + break; +#endif default: return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip); } @@ -413,7 +421,8 @@ const struct attribute_group tegra_soc_attr_group = { #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \ - IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC) + IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC) || \ + IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC) static ssize_t platform_show(struct device *dev, struct device_attribute *attr, char *buf) { diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index 2fad8b13a3b9..623848116b69 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -39,7 +39,8 @@ defined(CONFIG_ARCH_TEGRA_186_SOC) || \ defined(CONFIG_ARCH_TEGRA_194_SOC) || \ defined(CONFIG_ARCH_TEGRA_234_SOC) || \ - defined(CONFIG_ARCH_TEGRA_241_SOC) + defined(CONFIG_ARCH_TEGRA_241_SOC) || \ + defined(CONFIG_ARCH_TEGRA_264_SOC) static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset) { if (WARN_ON(!fuse->base)) @@ -802,3 +803,168 @@ const struct tegra_fuse_soc tegra241_fuse_soc = { .soc_attr_group = &tegra194_soc_attr_group, }; #endif + +#ifdef CONFIG_ARCH_TEGRA_264_SOC +static const struct nvmem_keepout tegra264_fuse_keepouts[] = { + { .start = 0x0019c, .end = 0x001a0 }, + { .start = 0x00308, .end = 0x00310 }, + { .start = 0x0032c, .end = 0x00334 }, + { .start = 0x00350, .end = 0x00354 }, + { .start = 0x00494, .end = 0x0049c }, + { .start = 0x0078c, .end = 0x00790 }, + { .start = 0x007a0, .end = 0x007a8 }, + { .start = 0x007dc, .end = 0x007e4 }, + { .start = 0x008d8, .end = 0x008dc }, + { .start = 0x0096c, .end = 0x00970 }, + { .start = 0x00974, .end = 0x0097c }, + { .start = 0x009f4, .end = 0x009f8 }, + { .start = 0x00a14, .end = 0x00a20 }, + { .start = 0x00a44, .end = 0x00a4c }, + { .start = 0x00a50, .end = 0x00a58 }, + { .start = 0x00a5c, .end = 0x00a64 }, + { .start = 0x00a68, .end = 0x00a70 }, + { .start = 0x00acc, .end = 0x00ad0 }, + { .start = 0x00b0c, .end = 0x00b18 }, + { .start = 0x00c80, .end = 0x00c8c }, + { .start = 0x00dac, .end = 0x00db4 }, + { .start = 0x00db8, .end = 0x00dbc }, + { .start = 0x00e0c, .end = 0x00e10 }, + { .start = 0x00fd0, .end = 0x01f00 }, + { .start = 0x01f1c, .end = 0x10064 }, + { .start = 0x10084, .end = 0x100a0 }, + { .start = 0x100a4, .end = 0x1019c }, + { .start = 0x101a0, .end = 0x101cc }, + { .start = 0x101d0, .end = 0x10308 }, + { .start = 0x10310, .end = 0x1055c }, + { .start = 0x1057c, .end = 0x106b0 }, + { .start = 0x106b4, .end = 0x11008 }, + { .start = 0x1100c, .end = 0x11018 }, + { .start = 0x11020, .end = 0x110b8 }, + { .start = 0x110c4, .end = 0x110c8 }, + { .start = 0x110e8, .end = 0x110ec }, + { .start = 0x110f0, .end = 0x11124 }, + { .start = 0x11128, .end = 0x11168 }, + { .start = 0x1116c, .end = 0x111b8 }, + { .start = 0x111bc, .end = 0x111e4 }, + { .start = 0x111e8, .end = 0x111ec }, + { .start = 0x111f0, .end = 0x1121c }, + { .start = 0x11250, .end = 0x1133c }, + { .start = 0x11340, .end = 0x113c8 }, + { .start = 0x113d0, .end = 0x11420 }, + { .start = 0x11430, .end = 0x11440 }, + { .start = 0x11444, .end = 0x11468 }, + { .start = 0x1146c, .end = 0x114a8 }, + { .start = 0x114ac, .end = 0x115cc }, + { .start = 0x115d0, .end = 0x115dc }, + { .start = 0x115e0, .end = 0x116b4 }, + { .start = 0x116bc, .end = 0x11740 }, + { .start = 0x11744, .end = 0x117b8 }, + { .start = 0x117bc, .end = 0x11810 }, + { .start = 0x11814, .end = 0x11850 }, + { .start = 0x11858, .end = 0x118a0 }, + { .start = 0x118ac, .end = 0x11b48 }, + { .start = 0x11b50, .end = 0x11b5c }, + { .start = 0x11b60, .end = 0x11bf8 }, + { .start = 0x11bfc, .end = 0x11c18 }, + { .start = 0x11c40, .end = 0x12000 }, + { .start = 0x12004, .end = 0x12010 }, + { .start = 0x12014, .end = 0x120fc }, + { .start = 0x1211c, .end = 0x12120 }, + { .start = 0x12124, .end = 0x12144 }, + { .start = 0x1214c, .end = 0x12300 }, + { .start = 0x12308, .end = 0x1236c }, + { .start = 0x12370, .end = 0x126ac }, + { .start = 0x126b0, .end = 0x12c60 }, + { .start = 0x12c64, .end = 0x12d94 }, + { .start = 0x12da4, .end = 0x13004 }, + { .start = 0x13008, .end = 0x1300c }, + { .start = 0x13010, .end = 0x13014 }, + { .start = 0x13018, .end = 0x13020 }, + { .start = 0x13064, .end = 0x13084 }, + { .start = 0x130a0, .end = 0x130a4 }, + { .start = 0x130b8, .end = 0x130c4 }, + { .start = 0x130c8, .end = 0x130e8 }, + { .start = 0x130ec, .end = 0x130f0 }, + { .start = 0x130fc, .end = 0x1311c }, + { .start = 0x13120, .end = 0x13128 }, + { .start = 0x13144, .end = 0x1314c }, + { .start = 0x13168, .end = 0x1316c }, + { .start = 0x1319c, .end = 0x131a0 }, + { .start = 0x131ac, .end = 0x131c0 }, + { .start = 0x131cc, .end = 0x131d0 }, + { .start = 0x131e4, .end = 0x131e8 }, + { .start = 0x131ec, .end = 0x131f0 }, + { .start = 0x1321c, .end = 0x13250 }, + { .start = 0x132f0, .end = 0x13310 }, + { .start = 0x1332c, .end = 0x13334 }, + { .start = 0x1333c, .end = 0x13344 }, + { .start = 0x13350, .end = 0x13354 }, + { .start = 0x1336c, .end = 0x13370 }, + { .start = 0x133ac, .end = 0x133b0 }, + { .start = 0x133c8, .end = 0x133d0 }, + { .start = 0x13420, .end = 0x13430 }, + { .start = 0x13440, .end = 0x13444 }, + { .start = 0x13468, .end = 0x13470 }, + { .start = 0x13494, .end = 0x1349c }, + { .start = 0x134a8, .end = 0x134ac }, + { .start = 0x13544, .end = 0x1354c }, + { .start = 0x1355c, .end = 0x1357c }, + { .start = 0x135cc, .end = 0x135e0 }, + { .start = 0x135e4, .end = 0x13608 }, + { .start = 0x1360c, .end = 0x13620 }, + { .start = 0x136ac, .end = 0x136bc }, + { .start = 0x136c0, .end = 0x136c8 }, + { .start = 0x13714, .end = 0x13718 }, + { .start = 0x13724, .end = 0x13728 }, + { .start = 0x1372c, .end = 0x13730 }, + { .start = 0x13734, .end = 0x1373c }, + { .start = 0x13740, .end = 0x13744 }, + { .start = 0x13754, .end = 0x13758 }, + { .start = 0x13760, .end = 0x13784 }, + { .start = 0x1378c, .end = 0x13790 }, + { .start = 0x137a0, .end = 0x137a8 }, + { .start = 0x137b8, .end = 0x137bc }, + { .start = 0x137dc, .end = 0x137e4 }, + { .start = 0x137ec, .end = 0x137f0 }, + { .start = 0x13800, .end = 0x13818 }, + { .start = 0x13820, .end = 0x13828 }, + { .start = 0x13830, .end = 0x13858 }, + { .start = 0x138a0, .end = 0x138b0 }, + { .start = 0x138d0, .end = 0x138dc }, + { .start = 0x1396c, .end = 0x13970 }, + { .start = 0x13974, .end = 0x1397c }, + { .start = 0x139f4, .end = 0x139f8 }, + { .start = 0x13a14, .end = 0x13a20 }, + { .start = 0x13a44, .end = 0x13a4c }, + { .start = 0x13a50, .end = 0x13a58 }, + { .start = 0x13a5c, .end = 0x13a64 }, + { .start = 0x13a68, .end = 0x13a70 }, + { .start = 0x13acc, .end = 0x13ad8 }, + { .start = 0x13b0c, .end = 0x13b18 }, + { .start = 0x13b48, .end = 0x13b50 }, + { .start = 0x13b5c, .end = 0x13b60 }, + { .start = 0x13bf8, .end = 0x13bfc }, + { .start = 0x13c18, .end = 0x13c40 }, + { .start = 0x13c60, .end = 0x13c64 }, + { .start = 0x13c74, .end = 0x13c8c }, + { .start = 0x13d94, .end = 0x13da4 }, + { .start = 0x13dac, .end = 0x13db4 }, + { .start = 0x13db8, .end = 0x13dbc }, + { .start = 0x13df4, .end = 0x13e04 }, + { .start = 0x13e0c, .end = 0x13e10 }, +}; + +static const struct tegra_fuse_info tegra264_fuse_info = { + .read = tegra30_fuse_read, + .size = 0x13eb8, +}; + +const struct tegra_fuse_soc tegra264_fuse_soc = { + .init = tegra30_fuse_init, + .info = &tegra264_fuse_info, + .keepouts = tegra264_fuse_keepouts, + .num_keepouts = ARRAY_SIZE(tegra264_fuse_keepouts), + .soc_attr_group = &tegra194_soc_attr_group, + .clk_suspend_on = false, +}; +#endif diff --git a/drivers/soc/tegra/fuse/fuse.h b/drivers/soc/tegra/fuse/fuse.h index 9fee6ad6ad9e..0fb97508db0a 100644 --- a/drivers/soc/tegra/fuse/fuse.h +++ b/drivers/soc/tegra/fuse/fuse.h @@ -125,7 +125,8 @@ extern const struct tegra_fuse_soc tegra186_fuse_soc; #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \ IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \ - IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC) + IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC) || \ + IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC) extern const struct attribute_group tegra194_soc_attr_group; #endif @@ -141,4 +142,8 @@ extern const struct tegra_fuse_soc tegra234_fuse_soc; extern const struct tegra_fuse_soc tegra241_fuse_soc; #endif +#ifdef CONFIG_ARCH_TEGRA_264_SOC +extern const struct tegra_fuse_soc tegra264_fuse_soc; +#endif + #endif diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index ea4dfe1994bd..4aece3370708 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -11,6 +11,7 @@ #define pr_fmt(fmt) "tegra-pmc: " fmt +#include <linux/acpi.h> #include <linux/arm-smccc.h> #include <linux/clk.h> #include <linux/clk-provider.h> @@ -2980,6 +2981,18 @@ static void tegra_pmc_reset_suspend_mode(void *data) pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY; } +static int tegra_pmc_acpi_probe(struct platform_device *pdev, struct tegra_pmc *pmc) +{ + pmc->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pmc->base)) + return PTR_ERR(pmc->base); + + tegra_pmc_reset_sysfs_init(pmc); + platform_set_drvdata(pdev, pmc); + + return 0; +} + static int tegra_pmc_probe(struct platform_device *pdev) { struct tegra_pmc *pmc; @@ -3004,6 +3017,9 @@ static int tegra_pmc_probe(struct platform_device *pdev) mutex_init(&pmc->powergates_lock); pmc->dev = &pdev->dev; + if (is_acpi_node(dev_fwnode(&pdev->dev))) + return tegra_pmc_acpi_probe(pdev, pmc); + err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node); if (err < 0) return dev_err_probe(&pdev->dev, err, "failed to parse DT\n"); @@ -4821,6 +4837,81 @@ static const struct tegra_pmc_soc tegra264_pmc_soc = { .max_wake_vectors = 4, }; +static const char * const tegra410_reset_sources[] = { + "SYS_RESET_N", /* 0x0 */ + "CSDC_RTC_XTAL", + "VREFRO_POWER_BAD", + "FMON_32K", + "FMON_OSC", + "POD_RTC", + "POD_IO", + "POD_PLUS_IO_SPLL", + "POD_PLUS_IO_VMON", /* 0x8 */ + "POD_PLUS_SOC", + "VMON_PLUS_UV", + "VMON_PLUS_OV", + "FUSECRC_FAULT", + "OSC_FAULT", + "BPMP_BOOT_FAULT", + "SCPM_BPMP_CORE_CLK", + "SCPM_PSC_SE_CLK", /* 0x10 */ + "VMON_SOC_MIN", + "VMON_SOC_MAX", + "NVJTAG_SEL_MONITOR", + "L0_RST_REQ_N", + "NV_THERM_FAULT", + "PSC_SW", + "POD_C2C_LPI_0", + "POD_C2C_LPI_1", /* 0x18 */ + "BPMP_FMON", + "FMON_SPLL_OUT", + "L1_RST_REQ_N", + "OCP_RECOVERY", + "AO_WDT_POR", + "BPMP_WDT_POR", + "RAS_WDT_POR", + "TOP_0_WDT_POR", /* 0x20 */ + "TOP_1_WDT_POR", + "TOP_2_WDT_POR", + "PSC_WDT_POR", + "OOBHUB_WDT_POR", + "MSS_SEQ_WDT_POR", + "SW_MAIN", + "L0L1_RST_OUT_N", + "HSM", /* 0x28 */ + "CSITE_SW", + "AO_WDT_DBG", + "BPMP_WDT_DBG", + "RAS_WDT_DBG", + "TOP_0_WDT_DBG", + "TOP_1_WDT_DBG", + "TOP_2_WDT_DBG", + "PSC_WDT_DBG", /* 0x30 */ + "TSC_0_WDT_DBG", + "TSC_1_WDT_DBG", + "OOBHUB_WDT_DBG", + "MSS_SEQ_WDT_DBG", + "L2_RST_REQ_N", + "L2_RST_OUT_N", + "SC7" +}; + +static const struct tegra_pmc_regs tegra410_pmc_regs = { + .rst_status = 0x8, + .rst_source_shift = 0x2, + .rst_source_mask = 0xfc, + .rst_level_shift = 0x0, + .rst_level_mask = 0x3, +}; + +static const struct tegra_pmc_soc tegra410_pmc_soc = { + .regs = &tegra410_pmc_regs, + .reset_sources = tegra410_reset_sources, + .num_reset_sources = ARRAY_SIZE(tegra410_reset_sources), + .reset_levels = tegra186_reset_levels, + .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels), +}; + static const struct of_device_id tegra_pmc_match[] = { { .compatible = "nvidia,tegra264-pmc", .data = &tegra264_pmc_soc }, { .compatible = "nvidia,tegra238-pmc", .data = &tegra238_pmc_soc }, @@ -4836,6 +4927,12 @@ static const struct of_device_id tegra_pmc_match[] = { { } }; +static const struct acpi_device_id tegra_pmc_acpi_match[] = { + { .id = "NVDA2016", .driver_data = (kernel_ulong_t)&tegra410_pmc_soc }, + { } +}; +MODULE_DEVICE_TABLE(acpi, tegra_pmc_acpi_match); + static void tegra_pmc_sync_state(struct device *dev) { struct tegra_pmc *pmc = dev_get_drvdata(dev); @@ -4887,6 +4984,7 @@ static struct platform_driver tegra_pmc_driver = { .name = "tegra-pmc", .suppress_bind_attrs = true, .of_match_table = tegra_pmc_match, + .acpi_match_table = tegra_pmc_acpi_match, #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM) .pm = &tegra_pmc_pm_ops, #endif |