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| author | Juergen Gross <jgross@suse.com> | 2026-07-03 13:24:26 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2026-07-17 11:30:36 +0200 |
| commit | f44da125bcecd78705ab506f6e18a4a5db1a35e1 (patch) | |
| tree | f31337011890c677ac566b215085a863c74247f4 | |
| parent | 1620ddc0dcefc6ffb85f4718086e880335d1a7f5 (diff) | |
| download | linux-next-f44da125bcecd78705ab506f6e18a4a5db1a35e1.tar.gz linux-next-f44da125bcecd78705ab506f6e18a4a5db1a35e1.zip | |
x86/featctl: Stop using 32-bit MSR interfaces
The 32-bit MSR interfaces rdmsr() and rdmsr_safe() are planned to be
removed. Use the related 64-bit variants instead.
Signed-off-by: Juergen Gross <jgross@suse.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Link: https://patch.msgid.link/20260703112426.1763049-1-jgross@suse.com
| -rw-r--r-- | arch/x86/kernel/cpu/feat_ctl.c | 25 |
1 files changed, 16 insertions, 9 deletions
diff --git a/arch/x86/kernel/cpu/feat_ctl.c b/arch/x86/kernel/cpu/feat_ctl.c index d69757246bde..10a92927a515 100644 --- a/arch/x86/kernel/cpu/feat_ctl.c +++ b/arch/x86/kernel/cpu/feat_ctl.c @@ -25,7 +25,8 @@ enum vmx_feature_leafs { static void init_vmx_capabilities(struct cpuinfo_x86 *c) { - u32 supported, funcs, ept, vpid, ign, low, high; + struct msr val; + u32 supported, funcs, ept, vpid; BUILD_BUG_ON(NVMXINTS != NR_VMX_FEATURE_WORDS); @@ -39,25 +40,31 @@ static void init_vmx_capabilities(struct cpuinfo_x86 *c) * as they exist on any CPU that supports VMX, i.e. we want the WARN if * the RDMSR faults. */ - rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, ign, supported); + rdmsrq(MSR_IA32_VMX_PROCBASED_CTLS, val.q); + supported = val.h; c->vmx_capability[PRIMARY_CTLS] = supported; - rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &ign, &supported); + rdmsrq_safe(MSR_IA32_VMX_PROCBASED_CTLS2, &val.q); + supported = val.h; c->vmx_capability[SECONDARY_CTLS] = supported; /* All 64 bits of tertiary controls MSR are allowed-1 settings. */ - rdmsr_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &low, &high); - c->vmx_capability[TERTIARY_CTLS_LOW] = low; - c->vmx_capability[TERTIARY_CTLS_HIGH] = high; + rdmsrq_safe(MSR_IA32_VMX_PROCBASED_CTLS3, &val.q); + c->vmx_capability[TERTIARY_CTLS_LOW] = val.l; + c->vmx_capability[TERTIARY_CTLS_HIGH] = val.h; - rdmsr(MSR_IA32_VMX_PINBASED_CTLS, ign, supported); - rdmsr_safe(MSR_IA32_VMX_VMFUNC, &ign, &funcs); + rdmsrq(MSR_IA32_VMX_PINBASED_CTLS, val.q); + supported = val.h; + rdmsrq_safe(MSR_IA32_VMX_VMFUNC, &val.q); + funcs = val.h; /* * Except for EPT+VPID, which enumerates support for both in a single * MSR, low for EPT, high for VPID. */ - rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, &ept, &vpid); + rdmsrq_safe(MSR_IA32_VMX_EPT_VPID_CAP, &val.q); + ept = val.l; + vpid = val.h; /* Pin, EPT, VPID and VM-Func are merged into a single word. */ WARN_ON_ONCE(supported >> 16); |