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| author | Mark Brown <broonie@kernel.org> | 2026-08-21 13:55:56 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2026-08-21 13:55:57 +0100 |
| commit | e9bf9bab14e35e5ae80ce66c0ab5a2c9a94a629f (patch) | |
| tree | 4487422151c7063afbff428bb636184f82381ea0 | |
| parent | 2948a8c5d1ddfc08374d0099d30c4742466fbbd7 (diff) | |
| parent | f5be25e697e0362103625b1b197af126ae4ba5f7 (diff) | |
| download | linux-next-e9bf9bab14e35e5ae80ce66c0ab5a2c9a94a629f.tar.gz linux-next-e9bf9bab14e35e5ae80ce66c0ab5a2c9a94a629f.zip | |
Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git
| -rw-r--r-- | drivers/soc/mediatek/mt8167-mmsys.h | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h index 001379373507..d579feee4212 100644 --- a/drivers/soc/mediatek/mt8167-mmsys.h +++ b/drivers/soc/mediatek/mt8167-mmsys.h @@ -10,29 +10,24 @@ #define MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0x06c #define MT8167_DITHER_MOUT_EN_RDMA0 0x1 -#define MT8167_DITHER_MOUT_EN_MASK 0x7 - #define MT8167_RDMA0_SOUT_DSI0 0x2 -#define MT8167_RDMA0_SOUT_MASK 0x3 - #define MT8167_DSI0_SEL_IN_RDMA0 0x1 -#define MT8167_DSI0_SEL_IN_MASK 0x3 static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = { MMSYS_ROUTE(OVL, 0, COLOR, 0, MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0, OVL0_MOUT_EN_COLOR0), MMSYS_ROUTE(DITHER, 0, RDMA, 0, - MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK, + MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0, MT8167_DITHER_MOUT_EN_RDMA0), MMSYS_ROUTE(OVL, 0, COLOR, 0, MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0, COLOR0_SEL_IN_OVL0), MMSYS_ROUTE(RDMA, 0, DSI, 0, - MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK, + MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_RDMA0, MT8167_DSI0_SEL_IN_RDMA0), MMSYS_ROUTE(RDMA, 0, DSI, 0, - MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK, + MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_DSI0, MT8167_RDMA0_SOUT_DSI0), }; |