diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2026-10-02 21:20:07 +0100 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2026-10-02 21:20:07 +0100 |
| commit | b7516f2f64fd5ac461eae470ca050fc0a5eea18f (patch) | |
| tree | a801727afc4e70b6a66ec1ef2f4960fa79118c40 | |
| parent | 00bdd4d4daaae140ff747475ef475facee61a950 (diff) | |
| parent | 96b35a1251dc9977967286623fd15fcef34feeb1 (diff) | |
| download | linux-next-b7516f2f64fd5ac461eae470ca050fc0a5eea18f.tar.gz linux-next-b7516f2f64fd5ac461eae470ca050fc0a5eea18f.zip | |
Merge branch 'riscv-soc-drivers-for-next' into riscv-soc-for-next
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
17 files changed, 1478 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml new file mode 100644 index 000000000000..db43e03fd60c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-per0crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-0 Clock and Reset Generator + +maintainers: + - Changhuang Liang <changhuang.liang@starfivetech.com> + +properties: + compatible: + const: starfive,jhb100-per0crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (25 MHz) + - description: PLL6 + - description: Configure 400MHz + - description: Configure 800MHZ + - description: Non Coherent NOC Initiator + - description: Non Coherent NOC Target + + clock-names: + items: + - const: osc + - const: pll6 + - const: cfg_400 + - const: cfg_800 + - const: ncnoc_init + - const: ncnoc_targ + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jhb100-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11a08000 { + compatible = "starfive,jhb100-per0crg"; + reg = <0x11a08000 0x1000>; + clocks = <&osc>, <&pll6>, <&sys0crg 71>, + <&sys0crg 72>, <&sys0crg 70>, + <&sys2crg 23>; + clock-names = "osc", "pll6", "cfg_400", + "cfg_800", "ncnoc_init", + "ncnoc_targ"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml new file mode 100644 index 000000000000..c72a355ceb34 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-per1crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-1 Clock and Reset Generator + +maintainers: + - Changhuang Liang <changhuang.liang@starfivetech.com> + +properties: + compatible: + const: starfive,jhb100-per1crg + + reg: + maxItems: 1 + + clocks: + items: + - description: PLL7 + - description: Non Coherent NOC Initiator + - description: Configure 800MHz + - description: Non Coherent NOC Target + - description: Configure 143MHz + + clock-names: + items: + - const: pll7 + - const: ncnoc_init + - const: cfg_800 + - const: ncnoc_targ + - const: cfg_143 + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jhb100-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11b40000 { + compatible = "starfive,jhb100-per1crg"; + reg = <0x11b40000 0x1000>; + clocks = <&pll7>, + <&sys0crg 68>, + <&sys0crg 69>, + <&sys2crg 19>, + <&sys2crg 22>; + clock-names = "pll7", "ncnoc_init", + "cfg_800", "ncnoc_targ", + "cfg_143"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per2crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per2crg.yaml new file mode 100644 index 000000000000..175654645221 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per2crg.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-per2crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-2 Clock and Reset Generator + +maintainers: + - Changhuang Liang <changhuang.liang@starfivetech.com> + +properties: + compatible: + const: starfive,jhb100-per2crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Non Coherent NOC Initiator + - description: Configure 400MHz + - description: Configure 125MHz + - description: GMAC2 RGMII RX + - description: GMAC2 RMII Reference + - description: GMAC3 SGMII TX + - description: GMAC3 SGMII RX + - description: Main Oscillator (25 MHz) + + clock-names: + items: + - const: ncnoc_init + - const: cfg_400 + - const: cfg_125 + - const: gmac2_rgmii_rx + - const: gmac2_rmii_ref + - const: gmac3_sgmii_tx + - const: gmac3_sgmii_rx + - const: osc + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jhb100-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11bc0000 { + compatible = "starfive,jhb100-per2crg"; + reg = <0x11bc0000 0x1000>; + clocks = <&sys0crg 52>, <&sys0crg 54>, <&sys0crg 55>, + <&per2_gmac2_rgmii_rx>, <&per2_gmac2_rmii_ref>, + <&per2_gmac3_sgmii_tx>, <&per2_gmac3_sgmii_rx>, + <&osc>; + clock-names = "ncnoc_init", "cfg_400", "cfg_125", + "gmac2_rgmii_rx", "gmac2_rmii_ref", + "gmac3_sgmii_tx", "gmac3_sgmii_rx", + "osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml new file mode 100644 index 000000000000..2c3b9f4146b5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-per3crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 Peripheral-3 Clock and Reset Generator + +maintainers: + - Changhuang Liang <changhuang.liang@starfivetech.com> + +properties: + compatible: + const: starfive,jhb100-per3crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Non Coherent NOC Initiator + - description: Non Coherent NOC Target + - description: Configure 125MHz + - description: GMAC0 RMII Reference clock + - description: GMAC1 SGMII TX + - description: GMAC1 SGMII RX + - description: Main Oscillator (25 MHz) + + clock-names: + items: + - const: ncnoc_init + - const: ncnoc_targ + - const: cfg_125 + - const: gmac0_rmii_rclki + - const: gmac1_sgmii_tx + - const: gmac1_sgmii_rx + - const: osc + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jhb100-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@11c40000 { + compatible = "starfive,jhb100-per3crg"; + reg = <0x11c40000 0x1000>; + clocks = <&sys0crg 65>, + <&sys1crg 18>, + <&sys1crg 19>, + <&per3_gmac0_rmii_rclki>, + <&per3_gmac1_sgmii_tx>, + <&per3_gmac1_sgmii_rx>, + <&osc>; + clock-names = "ncnoc_init", "ncnoc_targ", "cfg_125", + "gmac0_rmii_rclki", "gmac1_sgmii_tx", + "gmac1_sgmii_rx", "osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml new file mode 100644 index 000000000000..cf1b0175b158 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys0crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-0 Clock and Reset Generator + +maintainers: + - Changhuang Liang <changhuang.liang@starfivetech.com> + +properties: + compatible: + const: starfive,jhb100-sys0crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (25 MHz) + - description: PLL0 + - description: PLL1 + - description: PLL2 + + clock-names: + items: + - const: osc + - const: pll0 + - const: pll1 + - const: pll2 + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jhb100-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13000000 { + compatible = "starfive,jhb100-sys0crg"; + reg = <0x13000000 0x4000>; + clocks = <&osc>, <&pll0>, <&pll1>, + <&syspll 0>; + clock-names = "osc", "pll0", "pll1", "pll2"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml new file mode 100644 index 000000000000..70cbfa38c100 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys1crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-1 Clock and Reset Generator + +maintainers: + - Changhuang Liang <changhuang.liang@starfivetech.com> + +properties: + compatible: + const: starfive,jhb100-sys1crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (25 MHz) + - description: PLL0 + - description: PLL1 + - description: PLL2 + - description: PLL4 + - description: PLL5 + - description: NPU Non Coherent NOC Initiator + + clock-names: + items: + - const: osc + - const: pll0 + - const: pll1 + - const: pll2 + - const: pll4 + - const: pll5 + - const: npu_ncnoc_init + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jhb100-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13004000 { + compatible = "starfive,jhb100-sys1crg"; + reg = <0x13004000 0x4000>; + clocks = <&osc>, <&pll0>, <&pll1>, + <&syspll 0>, <&syspll 2>, + <&syspll 3>, <&sys0crg 61>; + clock-names = "osc", "pll0", "pll1", "pll2", + "pll4", "pll5", "npu_ncnoc_init"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml new file mode 100644 index 000000000000..a63809c72e2a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/starfive,jhb100-sys2crg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 System-2 Clock and Reset Generator + +maintainers: + - Changhuang Liang <changhuang.liang@starfivetech.com> + +properties: + compatible: + const: starfive,jhb100-sys2crg + + reg: + maxItems: 1 + + clocks: + items: + - description: Main Oscillator (25 MHz) + - description: PLL1 + - description: GPU0 Non Coherent NOC Initiator + - description: GPU1 Non Coherent NOC Initiator + + clock-names: + items: + - const: osc + - const: pll1 + - const: gpu0_ncnoc_init + - const: gpu1_ncnoc_init + + '#clock-cells': + const: 1 + description: + See <dt-bindings/clock/starfive,jhb100-crg.h> for valid indices. + + '#reset-cells': + const: 1 + description: + See <dt-bindings/reset/starfive,jhb100-crg.h> for valid indices. + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@13008000 { + compatible = "starfive,jhb100-sys2crg"; + reg = <0x13008000 0x4000>; + clocks = <&osc>, <&pll1>, <&sys0crg 73>, + <&sys0crg 74>; + clock-names = "osc", "pll1", "gpu0_ncnoc_init", + "gpu1_ncnoc_init"; + #clock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml new file mode 100644 index 000000000000..000f53acab34 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jhb100-syscon.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/starfive/starfive,jhb100-syscon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JHB100 SoC system controller + +maintainers: + - Kevin Xie <kevin.xie@starfivetech.com> + - Changhuang Liang <changhuang.liang@starfivetech.com> + +description: + The StarFive JHB100 SoC system controller contains MMIO registers used by + other hardware modules (e.g., PLL, eMMC, PCIe). These modules access + specific register offsets, bit masks, and shifts within the system + controller region for configuration and status. + +properties: + compatible: + items: + - enum: + - starfive,jhb100-b2h-syscon + - starfive,jhb100-gpu-syscon + - starfive,jhb100-h2b-syscon + - starfive,jhb100-host-syscon + - starfive,jhb100-husb-syscon + - starfive,jhb100-husbcmn-syscon + - starfive,jhb100-husbd-syscon + - starfive,jhb100-npu-syscon + - starfive,jhb100-pcieep-ecsr-syscon + - starfive,jhb100-pcierp-ecsr-syscon + - starfive,jhb100-pcierp-syscon + - starfive,jhb100-per0-syscon + - starfive,jhb100-per1-syscon + - starfive,jhb100-per2-syscon + - starfive,jhb100-per3-syscon + - starfive,jhb100-sfc-filter-syscon + - starfive,jhb100-strap-syscon + - starfive,jhb100-sys0-syscon + - starfive,jhb100-sys1-syscon + - starfive,jhb100-sys2-syscon + - starfive,jhb100-usb-syscon + - starfive,jhb100-vout-syscon + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - starfive,jhb100-per0-syscon + - starfive,jhb100-per1-syscon + - starfive,jhb100-sys0-syscon + then: + required: + - clocks + - '#clock-cells' + else: + properties: + clocks: false + '#clock-cells': false + + - if: + properties: + compatible: + contains: + const: starfive,jhb100-pcierp-syscon + then: + required: + - '#reset-cells' + else: + properties: + '#reset-cells': false + +additionalProperties: false + +examples: + - | + syscon@13010000 { + compatible = "starfive,jhb100-sys0-syscon", "syscon"; + reg = <0x13010000 0x2000>; + clocks = <&osc>; + #clock-cells = <1>; + }; + + syscon@13014000 { + compatible = "starfive,jhb100-sys1-syscon", "syscon"; + reg = <0x13014000 0x4000>; + }; + + syscon@11719000 { + compatible = "starfive,jhb100-pcierp-syscon", "syscon"; + reg = <0x11719000 0x1000>; + #reset-cells = <1>; + }; + +... diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index a2d65adffb80..b3b01fc38139 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -24,6 +24,7 @@ source "drivers/soc/renesas/Kconfig" source "drivers/soc/rockchip/Kconfig" source "drivers/soc/samsung/Kconfig" source "drivers/soc/sophgo/Kconfig" +source "drivers/soc/starfive/Kconfig" source "drivers/soc/sunxi/Kconfig" source "drivers/soc/tegra/Kconfig" source "drivers/soc/ti/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index c9e689080ceb..009f85ff891a 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -30,6 +30,7 @@ obj-y += renesas/ obj-y += rockchip/ obj-$(CONFIG_SOC_SAMSUNG) += samsung/ obj-y += sophgo/ +obj-y += starfive/ obj-y += sunxi/ obj-$(CONFIG_ARCH_TEGRA) += tegra/ obj-y += ti/ diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig new file mode 100644 index 000000000000..04b020083d3e --- /dev/null +++ b/drivers/soc/starfive/Kconfig @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-only +menu "StarFive SoC (System On Chip) specific Drivers" + +source "drivers/soc/starfive/socinfo/Kconfig" + +endmenu diff --git a/drivers/soc/starfive/Makefile b/drivers/soc/starfive/Makefile new file mode 100644 index 000000000000..ca1e609b8104 --- /dev/null +++ b/drivers/soc/starfive/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += socinfo/ diff --git a/drivers/soc/starfive/socinfo/Kconfig b/drivers/soc/starfive/socinfo/Kconfig new file mode 100644 index 000000000000..64f1b1e04d01 --- /dev/null +++ b/drivers/soc/starfive/socinfo/Kconfig @@ -0,0 +1,13 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config STARFIVE_JHB100_SOCINFO + bool "StarFive JHB100 SoC Information" + depends on ARCH_STARFIVE || COMPILE_TEST + select SOC_BUS + select MFD_CORE + select MFD_SYSCON + default y + help + Include support for the SoC bus socinfo for the StarFive JHB100 SoC + platforms to provide information about the SoC family and variant + to user space. diff --git a/drivers/soc/starfive/socinfo/Makefile b/drivers/soc/starfive/socinfo/Makefile new file mode 100644 index 000000000000..26c2bdf1de3b --- /dev/null +++ b/drivers/soc/starfive/socinfo/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_STARFIVE_JHB100_SOCINFO) += jhb100-socinfo.o diff --git a/drivers/soc/starfive/socinfo/jhb100-socinfo.c b/drivers/soc/starfive/socinfo/jhb100-socinfo.c new file mode 100644 index 000000000000..0a31cae9b4f5 --- /dev/null +++ b/drivers/soc/starfive/socinfo/jhb100-socinfo.c @@ -0,0 +1,105 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2025 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang <changhuang.liang@starfivetech.com> + */ + +#include <linux/bitfield.h> +#include <linux/device.h> +#include <linux/mfd/core.h> +#include <linux/mfd/syscon.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/sys_soc.h> + +#define JHB100_REV_ID 0x38 +#define JHB100_REV_ID_CHAR GENMASK(3, 2) +#define JHB100_REV_ID_NUM GENMASK(1, 0) + +/* + * The sys0 system controller region only contains the PLL controls, this + * revision ID register and a few debug registers, so instead of describing + * a child node in the devicetree the PLL device is instantiated from here. + */ +static const struct mfd_cell jhb100_sys0_syscon_cells[] = { + { .name = "jhb100-sys0-pll", }, +}; + +static void jhb100_socinfo_unregister(void *data) +{ + soc_device_unregister(data); +} + +static int jhb100_socinfo_probe(struct platform_device *pdev) +{ + struct soc_device_attribute *attrs; + struct device *dev = &pdev->dev; + struct soc_device *soc_dev; + struct regmap *regmap; + char rev_char; + u32 rev_id; + int ret; + + regmap = syscon_node_to_regmap(dev->of_node); + if (IS_ERR(regmap)) + return dev_err_probe(dev, PTR_ERR(regmap), + "failed to get syscon regmap\n"); + + ret = regmap_read(regmap, JHB100_REV_ID, &rev_id); + if (ret) + return dev_err_probe(dev, ret, "failed to read revision ID\n"); + + attrs = devm_kzalloc(dev, sizeof(*attrs), GFP_KERNEL); + if (!attrs) + return -ENOMEM; + + rev_char = FIELD_GET(JHB100_REV_ID_CHAR, rev_id) + 'A'; + + attrs->family = "JH"; + attrs->soc_id = "JHB100"; + attrs->revision = devm_kasprintf(dev, GFP_KERNEL, "%c%lu", rev_char, + FIELD_GET(JHB100_REV_ID_NUM, rev_id)); + if (!attrs->revision) + return -ENOMEM; + + soc_dev = soc_device_register(attrs); + if (IS_ERR(soc_dev)) + return dev_err_probe(dev, PTR_ERR(soc_dev), + "failed to register SoC device\n"); + + ret = devm_add_action_or_reset(dev, jhb100_socinfo_unregister, soc_dev); + if (ret) + return ret; + + ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, + jhb100_sys0_syscon_cells, + ARRAY_SIZE(jhb100_sys0_syscon_cells), + NULL, 0, NULL); + if (ret) + return dev_err_probe(dev, ret, "failed to add mfd cells\n"); + + dev_info(dev, "StarFive %s SoC rev(%s)\n", attrs->soc_id, attrs->revision); + + return 0; +} + +static const struct of_device_id jhb100_socinfo_of_match[] = { + { .compatible = "starfive,jhb100-sys0-syscon" }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_socinfo_driver = { + .probe = jhb100_socinfo_probe, + .driver = { + .name = "jhb100-socinfo", + .of_match_table = jhb100_socinfo_of_match, + }, +}; + +static int __init jhb100_socinfo_init(void) +{ + return platform_driver_register(&jhb100_socinfo_driver); +} +subsys_initcall(jhb100_socinfo_init); diff --git a/include/dt-bindings/clock/starfive,jhb100-crg.h b/include/dt-bindings/clock/starfive,jhb100-crg.h new file mode 100644 index 000000000000..4270bfa532e8 --- /dev/null +++ b/include/dt-bindings/clock/starfive,jhb100-crg.h @@ -0,0 +1,554 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Changhuang Liang <changhuang.liang@starfivetech.com> + * + */ + +#ifndef __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ +#define __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ + +/* SYS0PLL clocks */ +#define JHB100_SYS0PLL_PLL2_OUT 0 +#define JHB100_SYS0PLL_PLL3_OUT 1 +#define JHB100_SYS0PLL_PLL4_OUT 2 +#define JHB100_SYS0PLL_PLL5_OUT 3 + +/* PER0PLL clocks */ +#define JHB100_PER0PLL_PLL6_OUT 0 + +/* PER1PLL clocks */ +#define JHB100_PER1PLL_PLL7_OUT 0 + +/* SYS0CRG clocks */ +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_MAIN 17 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG 18 + +#define JHB100_SYS0CLK_PCIE_REF_CML 20 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_DATA_INIT 21 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_CFG_INIT 22 +#define JHB100_SYS0CLK_BMCPCIERP_NCNOC_TARG 23 + +#define JHB100_SYS0CLK_BMCPCIERP_PCU 26 +#define JHB100_SYS0CLK_HOSTSS0_NCNOC_CFG 27 +#define JHB100_SYS0CLK_HOSTSS0_NCNOC_DATA 28 +#define JHB100_SYS0CLK_HOSTSS0_PHY_SCAN_400 29 +#define JHB100_SYS0CLK_GPIO_ESPI0_EXT 30 + +#define JHB100_SYS0CLK_BMCUSB_NCNOC_INIT 34 +#define JHB100_SYS0CLK_BMCUSB_NCNOC_TARG 35 +#define JHB100_SYS0CLK_BMCUSB_SCANCLK 36 +#define JHB100_SYS0CLK_BMCUSB_480M_SCANCLK 37 + +#define JHB100_SYS0CLK_VCE_NCNOC_INIT 50 +#define JHB100_SYS0CLK_VCE_NCNOC_TARG 51 +#define JHB100_SYS0CLK_BMCPER2_NCNOC_INIT 52 +#define JHB100_SYS0CLK_BMCPER2_NCNOC_TARG 53 +#define JHB100_SYS0CLK_BMCPER2_CFG_400 54 +#define JHB100_SYS0CLK_BMCPER2_CFG_125 55 + +#define JHB100_SYS0CLK_HOSTSS1_NCNOC_DATA 58 +#define JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400 59 +#define JHB100_SYS0CLK_HOSTSS1_PHY_SCAN_400_ICG_BUF 60 +#define JHB100_SYS0CLK_NPU_NCNOC_INIT 61 +#define JHB100_SYS0CLK_VOUT_NCNOC_INIT 62 +#define JHB100_SYS0CLK_VOUT_AUX 63 + +#define JHB100_SYS0CLK_BMCPER3_NCNOC_INIT 65 +#define JHB100_SYS0CLK_HOSTUSB_NCNOC_INIT 66 +#define JHB100_SYS0CLK_HOSTUSBCMN_CFG_480 67 +#define JHB100_SYS0CLK_BMCPER1_NCNOC_INIT 68 +#define JHB100_SYS0CLK_BMCPER1_CFG_800 69 +#define JHB100_SYS0CLK_BMCPER0_NCNOC_INIT 70 +#define JHB100_SYS0CLK_BMCPER0_CFG_400 71 +#define JHB100_SYS0CLK_BMCPER0_CFG_800 72 +#define JHB100_SYS0CLK_GPU0_NCNOC_INIT 73 +#define JHB100_SYS0CLK_GPU1_NCNOC_INIT 74 + +/* SYS1CRG clocks */ +#define JHB100_SYS1CLK_APB_MAIN_SYS1 0 +#define JHB100_SYS1CLK_APB_SENSOR_ICG_BUF 1 + +#define JHB100_SYS1CLK_GPIO_ESPI1_EXT 5 + +#define JHB100_SYS1CLK_HOSTSS1_NCNOC_CFG 7 +#define JHB100_SYS1CLK_HOSTSS1_PHY_SCAN_1000_ICG_BUF 8 +#define JHB100_SYS1CLK_NPU_NCNOC_CFG 9 +#define JHB100_SYS1CLK_NPU_CORE_DIV 10 +#define JHB100_SYS1CLK_DOM_NPU_CORE_CLK 11 +#define JHB100_SYS1CLK_DOM_NPU_BUS_CLK 12 +#define JHB100_SYS1CLK_DOM_NPU_INIT_CLK 13 +#define JHB100_SYS1CLK_DOM_NPU_OSC_CLK 14 +#define JHB100_SYS1CLK_VOUT_NCNOC_TARG 15 +#define JHB100_SYS1CLK_VOUT_PIX0 16 +#define JHB100_SYS1CLK_VOUT_PIX1 17 +#define JHB100_SYS1CLK_BMCPER3_NCNOC_TARG 18 +#define JHB100_SYS1CLK_BMCPER3_CFG_125 19 + +/* SYS2CRG clocks */ +#define JHB100_SYS2CLK_JTAGM0_HCLK 3 +#define JHB100_SYS2CLK_JTAGM1_HCLK 4 +#define JHB100_SYS2CLK_JTAGM0_ATPG 5 +#define JHB100_SYS2CLK_JTAGM1_ATPG 6 +#define JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK 7 +#define JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK 8 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK 9 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG 10 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK 11 +#define JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK 12 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK 13 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG 14 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK 15 +#define JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK 16 +#define JHB100_SYS2CLK_HOSTUSB_NCNOC_TARG 17 +#define JHB100_SYS2CLK_HOSTUSBCMN_CFG_500 18 +#define JHB100_SYS2CLK_BMCPER1_NCNOC_TARG 19 +#define JHB100_SYS2CLK_BMCPER1_CFG_250 20 +#define JHB100_SYS2CLK_BMCPER1_CFG_143_DFT 21 +#define JHB100_SYS2CLK_BMCPER1_CFG_143 22 +#define JHB100_SYS2CLK_BMCPER0_NCNOC_TARG 23 +#define JHB100_SYS2CLK_GPU0_NCNOC_TARG 24 +#define JHB100_SYS2CLK_GPU0_BUS_CLK 25 +#define JHB100_SYS2CLK_GPU0_APB_CLK 26 +#define JHB100_SYS2CLK_GPU0_OSC_CLK 27 +#define JHB100_SYS2CLK_GPU1_NCNOC_TARG 28 +#define JHB100_SYS2CLK_GPU1_BUS_CLK 29 +#define JHB100_SYS2CLK_GPU1_APB_CLK 30 +#define JHB100_SYS2CLK_GPU1_OSC_CLK 31 +#define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0 32 +#define JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 33 + +/* PER0CRG clocks */ +#define JHB100_PER0CLK_CDR_I3C0 0 +#define JHB100_PER0CLK_CDR_I3C1 1 +#define JHB100_PER0CLK_CDR_I3C2 2 +#define JHB100_PER0CLK_CDR_I3C3 3 +#define JHB100_PER0CLK_CDR_I3C4 4 +#define JHB100_PER0CLK_CDR_I3C5 5 +#define JHB100_PER0CLK_CDR_I3C6 6 +#define JHB100_PER0CLK_CDR_I3C7 7 +#define JHB100_PER0CLK_CDR_I3C8 8 +#define JHB100_PER0CLK_CDR_I3C9 9 +#define JHB100_PER0CLK_CDR_I3C10 10 +#define JHB100_PER0CLK_CDR_I3C11 11 +#define JHB100_PER0CLK_CDR_I3C12 12 +#define JHB100_PER0CLK_CDR_I3C13 13 +#define JHB100_PER0CLK_CDR_I3C14 14 +#define JHB100_PER0CLK_CDR_I3C15 15 +#define JHB100_PER0CLK_200 16 +#define JHB100_PER0CLK_600_DIV6 17 +#define JHB100_PER0CLK_600_DIV6_DIV5 18 +#define JHB100_PER0CLK_TIMER0_DUALTIMER0 19 +#define JHB100_PER0CLK_TIMER1_DUALTIMER0 20 +#define JHB100_PER0CLK_TIMER0_DUALTIMER1 21 +#define JHB100_PER0CLK_TIMER1_DUALTIMER1 22 +#define JHB100_PER0CLK_TIMER0_DUALTIMER2 23 +#define JHB100_PER0CLK_TIMER1_DUALTIMER2 24 +#define JHB100_PER0CLK_1200_PH0_LVDS0 25 +#define JHB100_PER0CLK_1200_PH0_LVDS1 26 +#define JHB100_PER0CLK_1200_CORE0 27 +#define JHB100_PER0CLK_1200_CORE1 28 +#define JHB100_PER0CLK_1200_SHIFT90_LVDS0 29 +#define JHB100_PER0CLK_1200_SHIFT90_LVDS1 30 +#define JHB100_PER0CLK_1200_DIV5_CORE0 31 +#define JHB100_PER0CLK_1200_DIV5_CORE1 32 +#define JHB100_PER0CLK_PH0_LTPI0 33 + +#define JHB100_PER0CLK_PH0_LTPI1 35 + +#define JHB100_PER0CLK_PH90_LTPI0 37 + +#define JHB100_PER0CLK_PH90_LTPI1 39 + +#define JHB100_PER0CLK_240_CORE_LTPI0 41 + +#define JHB100_PER0CLK_240_CORE_LTPI1 43 + +#define JHB100_PER0CLK_AXI_DMA_I2C_INIT 45 +#define JHB100_PER0CLK_AXI_DMA_I3C_INIT 46 +#define JHB100_PER0CLK_AXI_DMA_UART_INIT 47 +#define JHB100_PER0CLK_CORE_DMAC0 48 +#define JHB100_PER0CLK_CORE_DMAC1 49 +#define JHB100_PER0CLK_CORE_DMAC2 50 + +#define JHB100_PER0CLK_HDR_TX_I3C0 78 +#define JHB100_PER0CLK_HDR_TX_I3C1 79 +#define JHB100_PER0CLK_HDR_TX_I3C2 80 +#define JHB100_PER0CLK_HDR_TX_I3C3 81 +#define JHB100_PER0CLK_HDR_TX_I3C4 82 +#define JHB100_PER0CLK_HDR_TX_I3C5 83 +#define JHB100_PER0CLK_HDR_TX_I3C6 84 +#define JHB100_PER0CLK_HDR_TX_I3C7 85 +#define JHB100_PER0CLK_HDR_TX_I3C8 86 +#define JHB100_PER0CLK_HDR_TX_I3C9 87 +#define JHB100_PER0CLK_HDR_TX_I3C10 88 +#define JHB100_PER0CLK_HDR_TX_I3C11 89 +#define JHB100_PER0CLK_HDR_TX_I3C12 90 +#define JHB100_PER0CLK_HDR_TX_I3C13 91 +#define JHB100_PER0CLK_HDR_TX_I3C14 92 +#define JHB100_PER0CLK_HDR_TX_I3C15 93 +#define JHB100_PER0CLK_CORE_I2C0 94 +#define JHB100_PER0CLK_CORE_I2C1 95 +#define JHB100_PER0CLK_CORE_I2C2 96 +#define JHB100_PER0CLK_CORE_I2C3 97 +#define JHB100_PER0CLK_CORE_I2C4 98 +#define JHB100_PER0CLK_CORE_I2C5 99 +#define JHB100_PER0CLK_CORE_I2C6 100 +#define JHB100_PER0CLK_CORE_I2C7 101 +#define JHB100_PER0CLK_CORE_I2C8 102 +#define JHB100_PER0CLK_CORE_I2C9 103 +#define JHB100_PER0CLK_CORE_I2C10 104 +#define JHB100_PER0CLK_CORE_I2C11 105 +#define JHB100_PER0CLK_CORE_I2C12 106 +#define JHB100_PER0CLK_CORE_I2C13 107 +#define JHB100_PER0CLK_CORE_I2C14 108 +#define JHB100_PER0CLK_CORE_I2C15 109 + +#define JHB100_PER0CLK_WDOGCLK_WDT0 126 +#define JHB100_PER0CLK_WDOGCLK_WDT1 127 +#define JHB100_PER0CLK_WDOGCLK_WDT2 128 +#define JHB100_PER0CLK_WDOGCLK_WDT3 129 +#define JHB100_PER0CLK_WDOGCLK_WDT_EXTERNAL 130 +#define JHB100_PER0CLK_SCLK_UART4 131 +#define JHB100_PER0CLK_SCLK_UART5 132 +#define JHB100_PER0CLK_SCLK_UART6 133 +#define JHB100_PER0CLK_SCLK_UART7 134 +#define JHB100_PER0CLK_SCLK_UART8 135 +#define JHB100_PER0CLK_SCLK_UART9 136 +#define JHB100_PER0CLK_SCLK_UART10 137 +#define JHB100_PER0CLK_SCLK_UART11 138 +#define JHB100_PER0CLK_SCLK_UART12 139 +#define JHB100_PER0CLK_SCLK_UART13 140 +#define JHB100_PER0CLK_SCLK_UART14 141 + +#define JHB100_PER0CLK_PCLK_DMA_UART_CFG 148 +#define JHB100_PER0CLK_PCLK_DMA_I2C_CFG 149 +#define JHB100_PER0CLK_PCLK_DMA_I3C_CFG 150 +#define JHB100_PER0CLK_PCLK_DUALTIMER0 151 +#define JHB100_PER0CLK_PCLK_DUALTIMER1 152 +#define JHB100_PER0CLK_PCLK_DUALTIMER2 153 + +#define JHB100_PER0CLK_HCLK_TRNG 156 +#define JHB100_PER0CLK_APB_I2C0 157 +#define JHB100_PER0CLK_APB_I2C1 158 +#define JHB100_PER0CLK_APB_I2C2 159 +#define JHB100_PER0CLK_APB_I2C3 160 +#define JHB100_PER0CLK_APB_I2C4 161 +#define JHB100_PER0CLK_APB_I2C5 162 +#define JHB100_PER0CLK_APB_I2C6 163 +#define JHB100_PER0CLK_APB_I2C7 164 +#define JHB100_PER0CLK_APB_I2C8 165 +#define JHB100_PER0CLK_APB_I2C9 166 +#define JHB100_PER0CLK_APB_I2C10 167 +#define JHB100_PER0CLK_APB_I2C11 168 +#define JHB100_PER0CLK_APB_I2C12 169 +#define JHB100_PER0CLK_APB_I2C13 170 +#define JHB100_PER0CLK_APB_I2C14 171 +#define JHB100_PER0CLK_APB_I2C15 172 +#define JHB100_PER0CLK_APB_I2CF0 173 +#define JHB100_PER0CLK_APB_I2CF1 174 +#define JHB100_PER0CLK_APB_I2CF2 175 +#define JHB100_PER0CLK_APB_I2CF3 176 +#define JHB100_PER0CLK_APB_I2CF4 177 +#define JHB100_PER0CLK_APB_I2CF5 178 +#define JHB100_PER0CLK_APB_I2CF6 179 +#define JHB100_PER0CLK_APB_I2CF7 180 +#define JHB100_PER0CLK_APB_I2CF8 181 +#define JHB100_PER0CLK_APB_I2CF9 182 +#define JHB100_PER0CLK_APB_I2CF10 183 +#define JHB100_PER0CLK_APB_I2CF11 184 +#define JHB100_PER0CLK_APB_I2CF12 185 +#define JHB100_PER0CLK_APB_I2CF13 186 +#define JHB100_PER0CLK_APB_I2CF14 187 +#define JHB100_PER0CLK_APB_I2CF15 188 +#define JHB100_PER0CLK_APB_I3C0 189 +#define JHB100_PER0CLK_APB_I3C1 190 +#define JHB100_PER0CLK_APB_I3C2 191 +#define JHB100_PER0CLK_APB_I3C3 192 +#define JHB100_PER0CLK_APB_I3C4 193 +#define JHB100_PER0CLK_APB_I3C5 194 +#define JHB100_PER0CLK_APB_I3C6 195 +#define JHB100_PER0CLK_APB_I3C7 196 +#define JHB100_PER0CLK_APB_I3C8 197 +#define JHB100_PER0CLK_APB_I3C9 198 +#define JHB100_PER0CLK_APB_I3C10 199 +#define JHB100_PER0CLK_APB_I3C11 200 +#define JHB100_PER0CLK_APB_I3C12 201 +#define JHB100_PER0CLK_APB_I3C13 202 +#define JHB100_PER0CLK_APB_I3C14 203 +#define JHB100_PER0CLK_APB_I3C15 204 +#define JHB100_PER0CLK_APB_UART0 205 +#define JHB100_PER0CLK_APB_UART1 206 +#define JHB100_PER0CLK_APB_UART2 207 +#define JHB100_PER0CLK_APB_UART3 208 +#define JHB100_PER0CLK_APB_UART4 209 +#define JHB100_PER0CLK_APB_UART5 210 +#define JHB100_PER0CLK_APB_UART6 211 +#define JHB100_PER0CLK_APB_UART7 212 +#define JHB100_PER0CLK_APB_UART8 213 +#define JHB100_PER0CLK_APB_UART9 214 +#define JHB100_PER0CLK_APB_UART10 215 +#define JHB100_PER0CLK_APB_UART11 216 +#define JHB100_PER0CLK_APB_UART12 217 +#define JHB100_PER0CLK_APB_UART13 218 +#define JHB100_PER0CLK_APB_UART14 219 +#define JHB100_PER0CLK_DMA_I3C0 220 +#define JHB100_PER0CLK_DMA_I3C1 221 +#define JHB100_PER0CLK_DMA_I3C2 222 +#define JHB100_PER0CLK_DMA_I3C3 223 +#define JHB100_PER0CLK_DMA_I3C4 224 +#define JHB100_PER0CLK_DMA_I3C5 225 +#define JHB100_PER0CLK_DMA_I3C6 226 +#define JHB100_PER0CLK_DMA_I3C7 227 +#define JHB100_PER0CLK_DMA_I3C8 228 +#define JHB100_PER0CLK_DMA_I3C9 229 +#define JHB100_PER0CLK_DMA_I3C10 230 +#define JHB100_PER0CLK_DMA_I3C11 231 +#define JHB100_PER0CLK_DMA_I3C12 232 +#define JHB100_PER0CLK_DMA_I3C13 233 +#define JHB100_PER0CLK_DMA_I3C14 234 +#define JHB100_PER0CLK_DMA_I3C15 235 +#define JHB100_PER0CLK_CORE_I3C0 236 +#define JHB100_PER0CLK_CORE_I3C1 237 +#define JHB100_PER0CLK_CORE_I3C2 238 +#define JHB100_PER0CLK_CORE_I3C3 239 +#define JHB100_PER0CLK_CORE_I3C4 240 +#define JHB100_PER0CLK_CORE_I3C5 241 +#define JHB100_PER0CLK_CORE_I3C6 242 +#define JHB100_PER0CLK_CORE_I3C7 243 +#define JHB100_PER0CLK_CORE_I3C8 244 +#define JHB100_PER0CLK_CORE_I3C9 245 +#define JHB100_PER0CLK_CORE_I3C10 246 +#define JHB100_PER0CLK_CORE_I3C11 247 +#define JHB100_PER0CLK_CORE_I3C12 248 +#define JHB100_PER0CLK_CORE_I3C13 249 +#define JHB100_PER0CLK_CORE_I3C14 250 +#define JHB100_PER0CLK_CORE_I3C15 251 +#define JHB100_PER0CLK_DMAC_AXI_PERIPH0_HS_CLK_I2C 252 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C0 253 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C1 254 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C2 255 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C3 256 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C4 257 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C5 258 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C6 259 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C7 260 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C8 261 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C9 262 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C10 263 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C11 264 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C12 265 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C13 266 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C14 267 +#define JHB100_PER0CLK_MAIN_ICG_EN_I3C15 268 +#define JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER0 269 +#define JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER1 270 +#define JHB100_PER0CLK_MAIN_ICG_EN_DUALTIMER2 271 +#define JHB100_PER0CLK_MAIN_ICG_EN_LTPI0 272 +#define JHB100_PER0CLK_MAIN_ICG_EN_LTPI1 273 +#define JHB100_PER0CLK_MAIN_ICG_EN_DMAC_I2C 274 +#define JHB100_PER0CLK_MAIN_ICG_EN_DMAC_I3C 275 +#define JHB100_PER0CLK_MAIN_ICG_EN_DMAC_UART 276 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL4 277 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL5 278 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL6 279 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL7 280 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL8 281 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL9 282 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL10 283 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL11 284 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL12 285 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL13 286 +#define JHB100_PER0CLK_MAIN_ICG_EN_SOL14 287 + +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C0 304 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C1 305 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C2 306 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C3 307 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C4 308 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C5 309 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C6 310 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C7 311 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C8 312 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C9 313 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C10 314 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C11 315 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C12 316 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C13 317 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C14 318 +#define JHB100_PER0CLK_MAIN_ICG_EN_I2C15 319 +#define JHB100_PER0CLK_MAIN_ICG_EN_WDT0 320 +#define JHB100_PER0CLK_MAIN_ICG_EN_WDT1 321 +#define JHB100_PER0CLK_MAIN_ICG_EN_WDT2 322 +#define JHB100_PER0CLK_MAIN_ICG_EN_WDT3 323 +#define JHB100_PER0CLK_MAIN_ICG_EN_WDT_EXTERNAL 324 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART4 325 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART5 326 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART6 327 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART7 328 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART8 329 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART9 330 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART10 331 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART11 332 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART12 333 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART13 334 +#define JHB100_PER0CLK_MAIN_ICG_EN_UART14 335 +#define JHB100_PER0CLK_MAIN_ICG_EN_LDO0 336 +#define JHB100_PER0CLK_MAIN_ICG_EN_LDO1 337 +#define JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_PERIPH0 338 +#define JHB100_PER0CLK_MAIN_ICG_EN_SENSORS_DMAC 339 +#define JHB100_PER0CLK_MAIN_ICG_EN_TRNG 340 + +/* PER1CRG clocks */ +#define JHB100_PER1CLK_100 0 +#define JHB100_PER1CLK_1 1 +#define JHB100_PER1CLK_200_DIVN0 2 +#define JHB100_PER1CLK_200_DIVN1 3 +#define JHB100_PER1CLK_200_DIVN2 4 +#define JHB100_PER1CLK_200_DIVN3 5 +#define JHB100_PER1CLK_200_CCLK_DIV 6 + +#define JHB100_PER1CLK_SGPIO0_PCLK 15 +#define JHB100_PER1CLK_SGPIO0_DCLK 16 +#define JHB100_PER1CLK_SGPIO1_PCLK 17 +#define JHB100_PER1CLK_SGPIO1_DCLK 18 + +#define JHB100_PER1CLK_EMMC0_BCLK 22 + +#define JHB100_PER1CLK_EMMC0_CCLK 25 + +#define JHB100_PER1CLK_DMAC1_1CH_CORE 29 + +#define JHB100_PER1CLK_DMAC1_1CH_ACLK 31 + +#define JHB100_PER1CLK_DMAC2_1CH_CORE 33 + +#define JHB100_PER1CLK_DMAC2_1CH_ACLK 35 + +#define JHB100_PER1CLK_DMAC3_1CH_CORE 37 + +#define JHB100_PER1CLK_DMAC3_1CH_ACLK 39 + +#define JHB100_PER1CLK_DMAC0_2CH_CORE 41 + +#define JHB100_PER1CLK_DMAC0_2CH_ACLK 43 + +#define JHB100_PER1CLK_UFS_REF 45 +#define JHB100_PER1CLK_UFS_300 46 +#define JHB100_PER1CLK_UFS_150 47 +#define JHB100_PER1CLK_UFS_400 48 +#define JHB100_PER1CLK_UFS_75 49 +#define JHB100_PER1CLK_UFS_37_5 50 +#define JHB100_PER1CLK_UFS_7_5 51 +#define JHB100_PER1CLK_UFS_1_875 52 +#define JHB100_PER1CLK_UFS_7_143 53 +#define JHB100_PER1CLK_UFS_3_5715 54 + +#define JHB100_PER1CLK_MAIN_ICG_EN_SFC0 63 +#define JHB100_PER1CLK_MAIN_ICG_EN_SFC1 64 +#define JHB100_PER1CLK_MAIN_ICG_EN_SFC2 65 +#define JHB100_PER1CLK_MAIN_ICG_EN_SPI0 66 +#define JHB100_PER1CLK_MAIN_ICG_EN_SGPIO0 67 +#define JHB100_PER1CLK_MAIN_ICG_EN_SGPIO1 68 +#define JHB100_PER1CLK_MAIN_ICG_EN_SENSORS_PERIPH1 69 +#define JHB100_PER1CLK_MAIN_ICG_EN_EMMC0 70 +#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC0 71 +#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC1 72 +#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SFC2 73 +#define JHB100_PER1CLK_MAIN_ICG_EN_DMAC_SPI0 74 +#define JHB100_PER1CLK_MAIN_ICG_EN_RAS 75 +#define JHB100_PER1CLK_MAIN_ICG_EN_UFS 76 + +/* PER2CRG clocks */ +#define JHB100_PER2CLK_300 0 +#define JHB100_PER2CLK_100 1 +#define JHB100_PER2CLK_50 2 +#define JHB100_PER2CLK_GMAC2_RMII_50 3 +#define JHB100_PER2CLK_CAN0_CORE_DIV 4 +#define JHB100_PER2CLK_CAN1_CORE_DIV 5 +#define JHB100_PER2CLK_CAN0_TIMER 6 +#define JHB100_PER2CLK_CAN1_TIMER 7 + +#define JHB100_PER2CLK_RTC_CORE_DIV 11 +#define JHB100_PER2CLK_GMAC2_RMII_MUX_DLY 12 +#define JHB100_PER2CLK_GMAC2_RMII_DIV 13 + +#define JHB100_PER2CLK_GMAC2_RGMII_125_MUX 15 +#define JHB100_PER2CLK_GMAC2_RGMII_DIV 16 +#define JHB100_PER2CLK_GMAC2_TX_MUX 17 +#define JHB100_PER2CLK_GMAC2_TX_180_BUF 18 +#define JHB100_PER2CLK_GMAC2_RX_MUX_DLY 19 +#define JHB100_PER2CLK_GMAC2_RX_180_BUF 20 +#define JHB100_PER2CLK_GMAC2_TXCK_MUX_DLY 21 +#define JHB100_PER2CLK_GMAC3_TX_125_MUX 22 +#define JHB100_PER2CLK_GMAC3_RX_125_MUX 23 +#define JHB100_PER2CLK_GMAC3_TX_DIV 24 +#define JHB100_PER2CLK_GMAC3_RX_DIV 25 +#define JHB100_PER2CLK_SENSORS_PERIPH2 26 + +#define JHB100_PER2CLK_FAN_TACH_PCLK 33 + +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_I 44 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_I 45 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_TX_180_I 46 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RX_180_I 47 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_PTP_REF_I 48 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_RMII_I 49 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_CSR_I 50 +#define JHB100_PER2CLK_ETHER0_RMIIANDRGMII_ACLK_I 51 +#define JHB100_PER2CLK_RMIIANDRGMII_IOMUX_GMAC2_TXCK 52 +#define JHB100_PER2CLK_ETHER1_SGMII_TX_I 53 +#define JHB100_PER2CLK_ETHER1_SGMII_RX_I 54 +#define JHB100_PER2CLK_ETHER1_SGMII_TX_125_I 55 +#define JHB100_PER2CLK_ETHER1_SGMII_RX_125_I 56 +#define JHB100_PER2CLK_ETHER1_SGMII_PTP_REF_I 57 +#define JHB100_PER2CLK_ETHER1_SGMII_CSR_I 58 +#define JHB100_PER2CLK_ETHER1_SGMII_ACLK_I 59 +#define JHB100_PER2CLK_ETHER1_SGMII_PHY_PCLK_I 60 +#define JHB100_PER2CLK_ETHER1_SGMII_REF_25_I 61 +#define JHB100_PER2CLK_MAIN_ICG_EN_CAN0 62 +#define JHB100_PER2CLK_MAIN_ICG_EN_CAN1 63 + +#define JHB100_PER2CLK_MAIN_ICG_EN_DMAC_8CH 65 +#define JHB100_PER2CLK_MAIN_ICG_EN_RTC_SCAN 66 +#define JHB100_PER2CLK_MAIN_ICG_EN_ADC0 67 +#define JHB100_PER2CLK_MAIN_ICG_EN_ADC1 68 +#define JHB100_PER2CLK_MAIN_ICG_EN_GMAC2 69 +#define JHB100_PER2CLK_MAIN_ICG_EN_GMAC3 70 + +/* PER3CRG clocks */ +#define JHB100_PER3CLK_300 0 +#define JHB100_PER3CLK_200 1 +#define JHB100_PER3CLK_GMAC1_PTP_REF 2 +#define JHB100_PER3CLK_GMAC1_TX_125_MUX 3 +#define JHB100_PER3CLK_GMAC1_TX 4 +#define JHB100_PER3CLK_GMAC1_RX_125_MUX 5 +#define JHB100_PER3CLK_GMAC1_RX 6 +#define JHB100_PER3CLK_GMAC0_PTP_REF 7 +#define JHB100_PER3CLK_GMAC0_RMII_PLL 8 +#define JHB100_PER3CLK_GMAC0_RMII_MUX 9 +#define JHB100_PER3CLK_GMAC0_RMII_MUX_DIV2 10 + +#define JHB100_PER3CLK_ETHER0_RMII_CLK_TX_I 17 +#define JHB100_PER3CLK_ETHER0_RMII_CLK_RX_I 18 +#define JHB100_PER3CLK_ETHER0_RMII_CLK_PTP_REF_I 19 +#define JHB100_PER3CLK_ETHER0_RMII_CLK_RMII_I 20 +#define JHB100_PER3CLK_ETHER0_RMII_CLK_CSR_I 21 +#define JHB100_PER3CLK_ETHER0_RMII_ACLK_I 22 +#define JHB100_PER3CLK_GMAC0_RMII_RCLKO 23 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_I 24 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_I 25 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_TX_125_I 26 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_RX_125_I 27 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_PTP_REF_I 28 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_REF_25_I 29 +#define JHB100_PER3CLK_ETHER0_SGMII_CLK_CSR_I 30 +#define JHB100_PER3CLK_ETHER0_SGMII_ACLK_I 31 +#define JHB100_PER3CLK_ETHER0_SGMII_PHY_PCLK_I 32 +#define JHB100_PER3CLK_MAIN_ICG_EN_SENSORS_PERIPH3 33 +#define JHB100_PER3CLK_MAIN_ICG_EN_PECI0 34 +#define JHB100_PER3CLK_MAIN_ICG_EN_PECI1 35 +#define JHB100_PER3CLK_MAIN_ICG_EN_GMAC0 36 +#define JHB100_PER3CLK_MAIN_ICG_EN_GMAC1 37 + +#endif /* __DT_BINDINGS_CLOCK_STARFIVE_JHB100_H__ */ diff --git a/include/dt-bindings/reset/starfive,jhb100-crg.h b/include/dt-bindings/reset/starfive,jhb100-crg.h new file mode 100644 index 000000000000..1489bb01c2bd --- /dev/null +++ b/include/dt-bindings/reset/starfive,jhb100-crg.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * Author: Changhuang Liang <changhuang.liang@starfivetech.com> + * + */ + +#ifndef __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ +#define __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ + +/* SYS0CRG resets */ +#define JHB100_SYS0RST_RESOURCE_ARB 0 +#define JHB100_SYS0RST_SYS0_IOMUX_PRESETN 1 +#define JHB100_SYS0RST_SYS0H_IOMUX_PRESETN 2 +#define JHB100_SYS0RST_RST_ADAPTOR_TIMEOUT_RSTN 3 +#define JHB100_SYS0RST_BMCPCIERP_RSTN_BUS 4 +#define JHB100_SYS0RST_BMCPCIERP_RSTN_CRG 5 +#define JHB100_SYS0RST_HOSTSS0_RSTN_BUS_ESPI 6 +#define JHB100_SYS0RST_HOSTSS0_RSTN_BUS_PCIE 7 +#define JHB100_SYS0RST_HOSTSS0_RSTN_CRG 8 +#define JHB100_SYS0RST_BMCPERIPH2_RSTN_CRG 9 +#define JHB100_SYS0RST_BMCPERIPH2_RSTN_BUS 10 +#define JHB100_SYS0RST_VCE_RSTN_CRG 11 +#define JHB100_SYS0RST_VCE_RSTN_BUS 12 +#define JHB100_SYS0RST_BMCUSB_RSTN_BUS 13 +#define JHB100_SYS0RST_BMCUSB_RSTN_CRG 14 + +/* SYS1CRG resets */ +#define JHB100_SYS1RST_SYS1_IOMUX_PRESETN 0 +#define JHB100_SYS1RST_MAIN_RSTN_CHIPTOP_SENSOR 1 +#define JHB100_SYS1RST_VOUT_RSTN_HOST0 2 +#define JHB100_SYS1RST_VOUT_RSTN_HOST1 3 +#define JHB100_SYS1RST_HOSTSS1_RSTN_BUS_ESPI 4 +#define JHB100_SYS1RST_HOSTSS1_RSTN_BUS_PCIE 5 +#define JHB100_SYS1RST_HOSTSS1_RSTN_CRG 6 +#define JHB100_SYS1RST_BMCPERIPH3_RSTN_CRG 7 +#define JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS 8 + +/* SYS2CRG resets */ +#define JHB100_SYS2RST_JTAG0_MST_WRAP_HRESETN 0 +#define JHB100_SYS2RST_JTAG0_MST_WRAP_APB_PRESETN 1 +#define JHB100_SYS2RST_JTAG1_MST_WRAP_HRESETN 2 +#define JHB100_SYS2RST_JTAG1_MST_WRAP_APB_PRESETN 3 +#define JHB100_SYS2RST_HUSBCMN_HOSTCMN_RSTN_BUS_NCNOC_INIT 4 +#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTCMN_CRG 5 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_BMC_TARG 6 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_HOST_TARG 7 +#define JHB100_SYS2RST_HUSBCMN_RSTN_BMC_CRG 8 +#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB0_CRG 9 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_BMC_TARG 10 +#define JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_HOST_TARG 11 +#define JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB1_CRG 12 +#define JHB100_SYS2RST_BMCPERIPH1_RSTN_CRG 13 +#define JHB100_SYS2RST_BMCPERIPH1_RSTN_BUS 14 +#define JHB100_SYS2RST_BMCPERIPH0_RSTN_CRG 15 +#define JHB100_SYS2RST_BMCPERIPH0_RSTN_BUS 16 +#define JHB100_SYS2RST_GPU0_RSTN_CRG 17 +#define JHB100_SYS2RST_GPU0_RSTN_BUS 18 +#define JHB100_SYS2RST_GPU0_HOST_PCIE_RST_N 19 +#define JHB100_SYS2RST_GPU1_RSTN_CRG 20 +#define JHB100_SYS2RST_GPU1_RSTN_BUS 21 +#define JHB100_SYS2RST_GPU1_HOST_PCIE_RST_N 22 + +/* PER0CRG resets */ +#define JHB100_PER0RST_MAIN_RSTN_UART4 0 +#define JHB100_PER0RST_MAIN_RSTN_UART5 1 +#define JHB100_PER0RST_MAIN_RSTN_UART6 2 +#define JHB100_PER0RST_MAIN_RSTN_UART7 3 +#define JHB100_PER0RST_MAIN_RSTN_UART8 4 +#define JHB100_PER0RST_MAIN_RSTN_UART9 5 +#define JHB100_PER0RST_MAIN_RSTN_UART10 6 +#define JHB100_PER0RST_MAIN_RSTN_UART11 7 +#define JHB100_PER0RST_MAIN_RSTN_UART12 8 +#define JHB100_PER0RST_MAIN_RSTN_UART13 9 +#define JHB100_PER0RST_MAIN_RSTN_UART14 10 +#define JHB100_PER0RST_MAIN_RSTN_I2C0 11 +#define JHB100_PER0RST_MAIN_RSTN_I2C1 12 +#define JHB100_PER0RST_MAIN_RSTN_I2C2 13 +#define JHB100_PER0RST_MAIN_RSTN_I2C3 14 +#define JHB100_PER0RST_MAIN_RSTN_I2C4 15 +#define JHB100_PER0RST_MAIN_RSTN_I2C5 16 +#define JHB100_PER0RST_MAIN_RSTN_I2C6 17 +#define JHB100_PER0RST_MAIN_RSTN_I2C7 18 +#define JHB100_PER0RST_MAIN_RSTN_I2C8 19 +#define JHB100_PER0RST_MAIN_RSTN_I2C9 20 +#define JHB100_PER0RST_MAIN_RSTN_I2C10 21 +#define JHB100_PER0RST_MAIN_RSTN_I2C11 22 +#define JHB100_PER0RST_MAIN_RSTN_I2C12 23 +#define JHB100_PER0RST_MAIN_RSTN_I2C13 24 +#define JHB100_PER0RST_MAIN_RSTN_I2C14 25 +#define JHB100_PER0RST_MAIN_RSTN_I2C15 26 +#define JHB100_PER0RST_MAIN_RSTN_I3C0 27 +#define JHB100_PER0RST_MAIN_RSTN_I3C1 28 +#define JHB100_PER0RST_MAIN_RSTN_I3C2 29 +#define JHB100_PER0RST_MAIN_RSTN_I3C3 30 +#define JHB100_PER0RST_MAIN_RSTN_I3C4 31 +#define JHB100_PER0RST_MAIN_RSTN_I3C5 32 +#define JHB100_PER0RST_MAIN_RSTN_I3C6 33 +#define JHB100_PER0RST_MAIN_RSTN_I3C7 34 +#define JHB100_PER0RST_MAIN_RSTN_I3C8 35 +#define JHB100_PER0RST_MAIN_RSTN_I3C9 36 +#define JHB100_PER0RST_MAIN_RSTN_I3C10 37 +#define JHB100_PER0RST_MAIN_RSTN_I3C11 38 +#define JHB100_PER0RST_MAIN_RSTN_I3C12 39 +#define JHB100_PER0RST_MAIN_RSTN_I3C13 40 +#define JHB100_PER0RST_MAIN_RSTN_I3C14 41 +#define JHB100_PER0RST_MAIN_RSTN_I3C15 42 +#define JHB100_PER0RST_MAIN_RSTN_WDT0 43 +#define JHB100_PER0RST_MAIN_RSTN_WDT1 44 +#define JHB100_PER0RST_MAIN_RSTN_WDT2 45 +#define JHB100_PER0RST_MAIN_RSTN_WDT3 46 +#define JHB100_PER0RST_MAIN_RSTN_WDT4 47 +#define JHB100_PER0RST_MAIN_RSTN_DUALTIMER0 48 +#define JHB100_PER0RST_MAIN_RSTN_DUALTIMER1 49 +#define JHB100_PER0RST_MAIN_RSTN_DUALTIMER2 50 +#define JHB100_PER0RST_MAIN_RSTN_TRNG 51 +#define JHB100_PER0RST_MAIN_RSTN_DMAC0 52 +#define JHB100_PER0RST_MAIN_RSTN_DMAC1 53 +#define JHB100_PER0RST_MAIN_RSTN_DMAC2 54 +#define JHB100_PER0RST_MAIN_RSTN_LTPI0 55 +#define JHB100_PER0RST_MAIN_RSTN_LTPI1 56 +#define JHB100_PER0RST_MAIN_RSTN_SOL4 57 +#define JHB100_PER0RST_MAIN_RSTN_SOL5 58 +#define JHB100_PER0RST_MAIN_RSTN_SOL6 59 +#define JHB100_PER0RST_MAIN_RSTN_SOL7 60 +#define JHB100_PER0RST_MAIN_RSTN_SOL8 61 +#define JHB100_PER0RST_MAIN_RSTN_SOL9 62 +#define JHB100_PER0RST_MAIN_RSTN_SOL10 63 +#define JHB100_PER0RST_MAIN_RSTN_SOL11 64 +#define JHB100_PER0RST_MAIN_RSTN_SOL12 65 +#define JHB100_PER0RST_MAIN_RSTN_SOL13 66 +#define JHB100_PER0RST_MAIN_RSTN_SOL14 67 +#define JHB100_PER0RST_MAIN_RSTN_LDO0 68 +#define JHB100_PER0RST_MAIN_RSTN_LDO1 69 +#define JHB100_PER0RST_MAIN_RSTN_PERIPH0_SENSORS 70 +#define JHB100_PER0RST_MAIN_RSTN_DMAC0_SENSORS 71 +#define JHB100_PER0RST_SYSCON_PRESETN 72 +#define JHB100_PER0RST_GPIO_IOMUX_PRESETN 73 +#define JHB100_PER0RST_UART_MUX_REG_WRAP 74 + +/* PER1CRG resets */ +#define JHB100_PER1RST_IOMUX_PRESETN 0 +#define JHB100_PER1RST_SYSCON_PRESETN 1 +#define JHB100_PER1RST_MAIN_RSTN_SFC0 2 +#define JHB100_PER1RST_MAIN_RSTN_SFC1 3 +#define JHB100_PER1RST_MAIN_RSTN_SFC2 4 +#define JHB100_PER1RST_MAIN_RSTN_SPI0 5 +#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_SENSORS 6 +#define JHB100_PER1RST_MAIN_RSTN_SGPIO0 7 +#define JHB100_PER1RST_MAIN_RSTN_SGPIO1 8 +#define JHB100_PER1RST_MAIN_RSTN_EMMC0 9 +#define JHB100_PER1RST_MAIN_RSTN_UFS 10 +#define JHB100_PER1RST_MAIN_RSTN_UFS_PHY 11 +#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC0 12 +#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC1 13 +#define JHB100_PER1RST_MAIN_RSTN_DMAC_SFC2 14 +#define JHB100_PER1RST_MAIN_RSTN_DMAC_SPI0 15 +#define JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS 16 + +/* PER2CRG resets */ +#define JHB100_PER2RST_IOMUX_PRESETN 0 +#define JHB100_PER2RST_POK_IOMUX_PRESETN 1 +#define JHB100_PER2RST_SYSREG_RSTN 2 +#define JHB100_PER2RST_MAIN_RSTN_CAN0 3 +#define JHB100_PER2RST_MAIN_RSTN_CAN1 4 +#define JHB100_PER2RST_FAN_TACH_PRESETN 5 +#define JHB100_PER2RST_MAIN_RSTN_GMAC2 6 +#define JHB100_PER2RST_MAIN_RSTN_GMAC3 7 +#define JHB100_PER2RST_MAIN_RSTN_DMAC_8CH 8 +#define JHB100_PER2RST_MAIN_RSTN_RTC 9 +#define JHB100_PER2RST_ADC0_PRESETN 10 +#define JHB100_PER2RST_ADC0_IOMUX_PRESETN 11 +#define JHB100_PER2RST_ADC1_PRESETN 12 +#define JHB100_PER2RST_ADC1_IOMUX_PRESETN 13 +#define JHB100_PER2RST_MAIN_RSTN_PERIPH2_SENSORS 14 + +/* PER3CRG resets */ +#define JHB100_PER3RST_SYSREG_RSTN 0 +#define JHB100_PER3RST_MAIN_RSTN_GMAC0 1 +#define JHB100_PER3RST_MAIN_RSTN_GMAC1 2 +#define JHB100_PER3RST_MAIN_RSTN_PECI0 3 +#define JHB100_PER3RST_MAIN_RSTN_PECI1 4 +#define JHB100_PER3RST_MAIN_RSTN_PERIPH3_SENSORS 5 +#define JHB100_PER3RST_IOMUX_PRESETN 6 + +/* PCIERP SYSCON resets */ +#define JHB100_PCIERP_SYSCONRST_PE2RST_OUT 0 + +#endif /* __DT_BINDINGS_RESET_STARFIVE_JHB100_CRG_H__ */ |