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| author | Dave Jiang <dave.jiang@intel.com> | 2026-09-18 08:31:36 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2026-09-18 08:31:36 -0700 |
| commit | 7faee05e3ce7582845f272a3141d85241ff2b35e (patch) | |
| tree | d3394e360236752eb8703c8dbb55747cf833fcdc | |
| parent | 9eb6419022d81aac6d1d9ead0e1865b451153da5 (diff) | |
| parent | b25af6afd2f26b455108bab03dfeba52378e8dd2 (diff) | |
| download | linux-next-7faee05e3ce7582845f272a3141d85241ff2b35e.tar.gz linux-next-7faee05e3ce7582845f272a3141d85241ff2b35e.zip | |
Merge branch 'for-7.4/cxl-fixes' into cxl-for-next
cxl/core: Skip einj_inject creation when devm_add_action_or_reset() fails
cxl/events: Return IRQ_NONE when no event is pending
cxl/region: Create node access attributes for CFMWS-only NUMA nodes
| -rw-r--r-- | drivers/cxl/core/port.c | 3 | ||||
| -rw-r--r-- | drivers/cxl/core/region.c | 15 | ||||
| -rw-r--r-- | drivers/cxl/pci.c | 5 |
3 files changed, 20 insertions, 3 deletions
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index a1edfe93db19..6024bc9c1376 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -846,7 +846,8 @@ static void cxl_debugfs_create_dport_dir(struct cxl_dport *dport) dir = cxl_debugfs_create_dir(dev_name(dport->dport_dev)); - devm_add_action_or_reset(dport_to_host(dport), remove_debugfs, dir); + if (devm_add_action_or_reset(dport_to_host(dport), remove_debugfs, dir)) + return; debugfs_create_file("einj_inject", 0200, dir, dport, &cxl_einj_inject_fops); diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c index f54acbf68e84..5ef0ca0694ff 100644 --- a/drivers/cxl/core/region.c +++ b/drivers/cxl/core/region.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* Copyright(c) 2022 Intel Corporation. All rights reserved. */ +#include <linux/acpi.h> #include <linux/memregion.h> #include <linux/genalloc.h> #include <linux/debugfs.h> @@ -2631,7 +2632,19 @@ static bool cxl_region_update_coordinates(struct cxl_region *cxlr, int nid) for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) { if (cxlr->coord[i].read_bandwidth) { - node_update_perf_attrs(nid, &cxlr->coord[i], i); + /* + * A CFMWS-only node (not backed by a real SRAT pxm) + * has no HMAT memory_target, so hmat_callback() + * never created the access attributes for it: + * create them here instead of only updating them. + * This is called at most once per node (see + * nodemask_region_seen), so the attributes are not + * created twice. + */ + if (!acpi_node_backed_by_real_pxm(nid)) + node_set_perf_attrs(nid, &cxlr->coord[i], i); + else + node_update_perf_attrs(nid, &cxlr->coord[i], i); cset++; } } diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index c7c91e8dc51d..8b560cae91f2 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -515,6 +515,7 @@ static irqreturn_t cxl_event_thread(int irq, void *id) struct cxl_dev_id *dev_id = id; struct cxl_dev_state *cxlds = dev_id->cxlds; struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); + bool handled = false; u32 status; do { @@ -527,11 +528,13 @@ static irqreturn_t cxl_event_thread(int irq, void *id) status &= CXLDEV_EVENT_STATUS_ALL; if (!status) break; + + handled = true; cxl_mem_get_event_records(mds, status); cond_resched(); } while (status); - return IRQ_HANDLED; + return handled ? IRQ_HANDLED : IRQ_NONE; } static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting) |