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| author | Matheus Tagliari <mptagliari@gmail.com> | 2026-10-22 08:47:46 -0300 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2026-10-27 14:11:37 -0400 |
| commit | 505cb85d38eebcea3540e3917fc169bbb5e2597c (patch) | |
| tree | 74625317c61d1c0f61fb4f7ffb2680a635726292 | |
| parent | d6048b741ad18e13f3504632c8f8c74accf5c1e4 (diff) | |
| download | linux-next-505cb85d38eebcea3540e3917fc169bbb5e2597c.tar.gz linux-next-505cb85d38eebcea3540e3917fc169bbb5e2597c.zip | |
drm/radeon: process the VCE interrupt on SI and Trinity
radeon_vce_fence_emit() ends every VCE fence with VCE_CMD_TRAP, which
raises the VCE trap interrupt (IH src_id 167). cik_irq_process()
handles it by calling radeon_fence_process() for the matching VCE ring,
but si_irq_process() and evergreen_irq_process(), which serve the other
ASICs with VCE1 (SI and Trinity/Richland), have no case for it.
Add the same handling. The trap interrupt is not enabled on these
ASICs yet, so this does not change behaviour on its own; the next patch
enables it.
The SI part was tested together with the next patch. The Trinity part
mirrors the CIK and SI code and has not been tested on Trinity/Richland
hardware.
Fixes: a918efab631a ("drm/radeon: add VCE 1.0 support v4")
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Matheus Tagliari <mptagliari@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/si.c | 14 |
2 files changed, 28 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 3cbc6eedbf66..eb94916c8f68 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c @@ -4847,6 +4847,20 @@ restart_ih: drm_dbg(ddev, "IH: UVD int: 0x%08x\n", src_data); radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); break; + case 167: /* VCE */ + drm_dbg(ddev, "IH: VCE int: 0x%08x\n", src_data); + switch (src_data) { + case 0: + radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX); + break; + case 1: + radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX); + break; + default: + drm_err(ddev, "Unhandled interrupt: %d %d\n", src_id, src_data); + break; + } + break; case 146: case 147: addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 4681ff28630a..af3c4026d183 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -6347,6 +6347,20 @@ restart_ih: DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); break; + case 167: /* VCE */ + DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data); + switch (src_data) { + case 0: + radeon_fence_process(rdev, TN_RING_TYPE_VCE1_INDEX); + break; + case 1: + radeon_fence_process(rdev, TN_RING_TYPE_VCE2_INDEX); + break; + default: + DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); + break; + } + break; case 146: case 147: addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR); |