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| author | Karthik Poosa <karthik.poosa@intel.com> | 2026-10-15 12:44:31 +0530 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2026-10-15 10:22:25 -0400 |
| commit | 32b98ee8d317bcb8a8a9fb4f715e7889bcf7ea9f (patch) | |
| tree | 4d8c7848b4a4dca817c3ccc98c9a15f1f5ab8f2b | |
| parent | ae4cd659d22dc00a6e9bf1802485e6ea5c1f74e2 (diff) | |
| download | linux-next-32b98ee8d317bcb8a8a9fb4f715e7889bcf7ea9f.tar.gz linux-next-32b98ee8d317bcb8a8a9fb4f715e7889bcf7ea9f.zip | |
drm/xe/hwmon: add PCIe temperature support for CRI
Add the PCIe temperature sensor offset in READ_THERMAL_DATA for CRI.
Refactor PCIe temperature handling to use platform-specific sensor
indices and derive the mailbox group and byte offset from the sensor
index, eliminating special-case decoding logic.
v2:
- Remove variables group and byte variables in get_pcie_temp().
- Change xe_hwmon_pcie_temp_index() to take a const struct xe_hwmon *.
Signed-off-by: Karthik Poosa <karthik.poosa@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20261015071434.1063785-14-karthik.poosa@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
| -rw-r--r-- | drivers/gpu/drm/xe/xe_hwmon.c | 28 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pcode_api.h | 2 |
2 files changed, 20 insertions, 10 deletions
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c index 97d298786073..04063ff5bf88 100644 --- a/drivers/gpu/drm/xe/xe_hwmon.c +++ b/drivers/gpu/drm/xe/xe_hwmon.c @@ -107,12 +107,15 @@ enum sensor_attr_power { #define PWR_ATTR_TO_STR(attr) (((attr) == hwmon_power_max) ? "PL1" : "PL2") -/* Index of memory controller in READ_THERMAL_DATA output */ +/* Sensor byte indices in READ_THERMAL_DATA output for BMG. */ #define TEMP_INDEX_MCTRL 2 +#define TEMP_INDEX_PCIE 10 +#define BMG_G21_TEMP_INDEX_PCIE 8 -/* On CRI the memory controller temperatures are READ_THERMAL_DATA bytes 16..19. */ +/* Sensor byte indices in READ_THERMAL_DATA output for CRI. */ #define CRI_TEMP_INDEX_MCTRL 16 #define CRI_TEMP_MCTRL_COUNT 4 +#define CRI_TEMP_INDEX_PCIE 20 /* Mailbox sentinel reported for an unavailable temperature sensor */ #define TEMP_MBX_INVALID 0xFF @@ -1055,21 +1058,30 @@ static int get_mc_temp(struct xe_hwmon *hwmon, long *val) return 0; } -static int get_pcie_temp(struct xe_hwmon *hwmon, long *val) +static u8 xe_hwmon_pcie_temp_index(const struct xe_hwmon *hwmon) +{ + if (hwmon->xe->info.platform == XE_CRESCENTISLAND) + return CRI_TEMP_INDEX_PCIE; + + if (hwmon->xe->info.subplatform == XE_SUBPLATFORM_BATTLEMAGE_G21) + return BMG_G21_TEMP_INDEX_PCIE; + + return TEMP_INDEX_PCIE; +} + +static int get_pcie_temp(const struct xe_hwmon *hwmon, long *val) { struct xe_tile *root_tile = xe_device_get_root_tile(hwmon->xe); u32 data = 0; int ret; ret = xe_pcode_read(root_tile, PCODE_MBOX(PCODE_THERMAL_INFO, READ_THERMAL_DATA, - PCIE_SENSOR_GROUP_ID), &data, NULL); + xe_hwmon_pcie_temp_index(hwmon) / sizeof(data)), + &data, NULL); if (ret) return ret; - /* Sensor offset is different for G21 */ - if (hwmon->xe->info.subplatform != XE_SUBPLATFORM_BATTLEMAGE_G21) - data = REG_FIELD_GET(PCIE_SENSOR_MASK, data); - + data >>= (xe_hwmon_pcie_temp_index(hwmon) % sizeof(data)) * BITS_PER_BYTE; data = REG_FIELD_GET(TEMP_MASK, data); if (!mbx_temp_valid(hwmon, data)) { drm_dbg(&hwmon->xe->drm, "PCIe temperature not available\n"); diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h index 94575c476e3d..00c4fc7d0124 100644 --- a/drivers/gpu/drm/xe/xe_pcode_api.h +++ b/drivers/gpu/drm/xe/xe_pcode_api.h @@ -58,8 +58,6 @@ #define READ_THERMAL_LIMITS 0x0 #define READ_THERMAL_CONFIG 0x1 #define READ_THERMAL_DATA 0x2 -#define PCIE_SENSOR_GROUP_ID 0x2 -#define PCIE_SENSOR_MASK REG_GENMASK(31, 16) #define PCODE_LATE_BINDING 0x5C #define GET_CAPABILITY_STATUS 0x0 |