diff options
| author | Jim Quinlan <james.quinlan@broadcom.com> | 2026-09-11 19:35:31 -0400 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2026-10-14 13:33:23 -0500 |
| commit | 2a3c8e29ee4edd3bc3005cfdd0bf3449336241fd (patch) | |
| tree | 81ee03b14e9278ffd531904472ae6b4974254255 | |
| parent | 2ed8567ad8cb675b11a6cdd5e5d54fb4efe32a7b (diff) | |
| download | linux-next-2a3c8e29ee4edd3bc3005cfdd0bf3449336241fd.tar.gz linux-next-2a3c8e29ee4edd3bc3005cfdd0bf3449336241fd.zip | |
PCI: brcmstb: Declare and assign flag IS_BMIPS
Eliminate is_bmips(), which evaluates SoC chip IDs, and instead declare and
use CFG_FLG_IS_BMIPS, a flag that indicates the SoC employs a CPU with a
variant of the MIPS-1 ISA.
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://patch.msgid.link/20260911233541.1650895-7-james.quinlan@broadcom.com
| -rw-r--r-- | drivers/pci/controller/pcie-brcmstb.c | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 8a2dab31650a..9a0882cb0ca0 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -300,7 +300,8 @@ struct inbound_win { #define CFG_FLG_HAS_PHY BIT(0) /* The SoC PCIe HW can dump to the console PCIe error info */ #define CFG_FLG_HAS_ERR_REPORT BIT(1) - +/* SoC uses a Broadcom variant of the MIPS-1 ISA */ +#define CFG_FLG_IS_BMIPS BIT(2) struct pcie_cfg_data { const int *offsets; @@ -361,11 +362,6 @@ struct brcm_pcie { spinlock_t bridge_lock; }; -static inline bool is_bmips(const struct brcm_pcie *pcie) -{ - return pcie->cfg->soc_base == BCM7435 || pcie->cfg->soc_base == BCM7425; -} - static int brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie, u32 val) { unsigned long flags; @@ -1176,7 +1172,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return ret; tmp = readl(base + HARD_DEBUG(pcie)); - if (is_bmips(pcie)) + if (BFLAG(pcie, IS_BMIPS)) tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; else tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK; @@ -1189,7 +1185,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it * is encoded as 0=Rsvd, 1=128, 2=256, 3=512. */ - if (is_bmips(pcie)) + if (BFLAG(pcie, IS_BMIPS)) burst = 0x1; /* 256 bytes */ else if (pcie->cfg->soc_base == BCM2711) burst = 0x0; /* 128 bytes */ @@ -2001,6 +1997,7 @@ static const struct pcie_cfg_data bcm7425_cfg = { .num_inbound_wins = 3, .quirks = CFG_QUIRK_OB_WIN_32BIT_ADDR | CFG_QUIRK_OB_WIN_MAXSZ_128MB, + .flags = CFG_FLG_IS_BMIPS, }; static const struct pcie_cfg_data bcm7435_cfg = { @@ -2011,6 +2008,7 @@ static const struct pcie_cfg_data bcm7435_cfg = { .num_inbound_wins = 3, .quirks = CFG_QUIRK_OB_WIN_32BIT_ADDR | CFG_QUIRK_OB_WIN_MAXSZ_128MB, + .flags = CFG_FLG_IS_BMIPS, }; static const struct pcie_cfg_data bcm7216_cfg = { |