summaryrefslogtreecommitdiff
path: root/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
blob: 0185045c76309df8da4417bd91274d67b96ecf29 (plain) (blame)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2017 Microsemi Corporation */

/dts-v1/;

#include "ocelot.dtsi"

/ {
	compatible = "mscc,ocelot-pcb123", "mscc,ocelot";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0e000000>;
	};
};

&uart0 {
	status = "okay";
};

&uart2 {
	status = "okay";
};

&spi {
	status = "okay";

	flash@0 {
		compatible = "macronix,mx25l25635f", "jedec,spi-nor";
		spi-max-frequency = <20000000>;
		reg = <0>;
	};
};

&i2c {
	clock-frequency = <100000>;
	i2c-sda-hold-time-ns = <300>;
	status = "okay";
};

&mdio0 {
	status = "okay";
};

&port0 {
	status = "okay";
	phy-handle = <&phy0>;
	phy-mode = "internal";
};

&port1 {
	status = "okay";
	phy-handle = <&phy1>;
	phy-mode = "internal";
};

&port2 {
	status = "okay";
	phy-handle = <&phy2>;
	phy-mode = "internal";
};

&port3 {
	status = "okay";
	phy-handle = <&phy3>;
	phy-mode = "internal";
};