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|
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/renesas,5p35023.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas 5p35023 VersaClock 3 programmable I2C clock generator
maintainers:
- Biju Das <biju.das.jz@bp.renesas.com>
description: |
The 5P35023 is a VersaClock programmable clock generator and
is designed for low-power, consumer, and high-performance PCI
express applications. The 5P35023 device is a three PLL
architecture design, and each PLL is individually programmable
and allowing for up to 6 unique frequency outputs.
An internal OTP memory allows the user to store the configuration
in the device. After power up, the user can change the device register
settings through the I2C interface when I2C mode is selected.
The driver can read a full register map from the DT, and will use that
register map to initialize the attached part (via I2C) when the system
boots. Any configuration not supported by the common clock framework
must be done via the full register map, including optimized settings.
Link to datasheet:
https://www.renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator
properties:
compatible:
enum:
- renesas,5p35023
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
maxItems: 1
renesas,settings:
description: Optional, complete register map of the device.
Optimized settings for the device must be provided in full
and are written during initialization.
$ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 37
required:
- compatible
- reg
- '#clock-cells'
- clocks
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
versa3: clock-generator@68 {
compatible = "renesas,5p35023";
reg = <0x68>;
#clock-cells = <1>;
clocks = <&x1_x2>;
renesas,settings = [
80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
80 b0 45 c4 95
];
assigned-clocks = <&versa3 0>, <&versa3 1>,
<&versa3 2>, <&versa3 3>,
<&versa3 4>, <&versa3 5>;
assigned-clock-rates = <12288000>, <25000000>,
<12000000>, <11289600>,
<11289600>, <24000000>;
};
};
|
