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2025-02-16spi: atmel-quadspi: remove references to runtime PM on error pathClaudiu Beznea
There is no need to call runtime PM put APIs on error path of `atmel_qspi_sama7g5_transfer()` as the caller (`atmel_qspi_exec_op()`) of it will take care of this if needed. Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Durai Manickam KR <durai.manickamkr@microchip.com> Reported-by: Alexander Dahl <ada@thorsis.com> Closes: https://lore.kernel.org/linux-spi/20250109-carat-festivity-5f088e1add3c@thorsis.com/ [ csokas.bence: Rebase and clarify msg, fix/add tags ] Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20250207122145.162183-2-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2025-02-03spi: atmel-quadspi: Fix warning in doc-commentBence Csókás
The doc-comment for `struct atmel_qspi_pcal` had a typo in one of the struct members' name, causing a warning with the `W=1` option. Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202501311707.Ltj0qXse-lkp@intel.com/ Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20250203151249.79876-2-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2025-01-09spi: atmel-quadspi: Update to current device naming terminologyAlexander Dahl
For v6.9 the spi subsystem changed the terminology to host and target devices, see commit 99769a52464d ("spi: Update the "master/slave" terminology in documentation") for reference. Support for SAMA7G5 was forward ported recently from an old vendor branch before that terminology change, so naming for the new struct member is adapted to follow the current scheme. Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://patch.msgid.link/20250109094843.36014-1-ada@thorsis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2025-01-06spi: atmel-quadspi: Use devm_ clock managementBence Csókás
Clean up error handling by using the new devm_ clock handling functions. This should make it easier to add new code, as we can eliminate the "goto ladder" in probe(). Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20241219142851.430959-1-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2025-01-06spi: atmel-qspi: Memory barriers after memory-mapped I/OBence Csókás
The QSPI peripheral control and status registers are accessible via the SoC's APB bus, whereas MMIO transactions' data travels on the AHB bus. Microchip documentation and even sample code from Atmel emphasises the need for a memory barrier before the first MMIO transaction to the AHB-connected QSPI, and before the last write to its registers via APB. This is achieved by the following lines in `atmel_qspi_transfer()`: /* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */ (void)atmel_qspi_read(aq, QSPI_IFR); However, the current documentation makes no mention to synchronization requirements in the other direction, i.e. after the last data written via AHB, and before the first register access on APB. In our case, we were facing an issue where the QSPI peripheral would cease to send any new CSR (nCS Rise) interrupts, leading to a timeout in `atmel_qspi_wait_for_completion()` and ultimately this panic in higher levels: ubi0 error: ubi_io_write: error -110 while writing 63108 bytes to PEB 491:128, written 63104 bytes After months of extensive research of the codebase, fiddling around the debugger with kgdb, and back-and-forth with Microchip, we came to the conclusion that the issue is probably that the peripheral is still busy receiving on AHB when the LASTXFER bit is written to its Control Register on APB, therefore this write gets lost, and the peripheral still thinks there is more data to come in the MMIO transfer. This was first formulated when we noticed that doubling the write() of QSPI_CR_LASTXFER seemed to solve the problem. Ultimately, the solution is to introduce memory barriers after the AHB-mapped MMIO transfers, to ensure ordering. Fixes: d5433def3153 ("mtd: spi-nor: atmel-quadspi: Add spi-mem support to atmel-quadspi") Cc: Hari.PrasathGE@microchip.com Cc: Mahesh.Abotula@microchip.com Cc: Marco.Cardellini@microchip.com Cc: stable@vger.kernel.org # c0a0203cf579: ("spi: atmel-quadspi: Create `atmel_qspi_ops`"...) Cc: stable@vger.kernel.org # 6.x.y Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20241219091258.395187-1-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-18spi: atmel-quadspi: Factor out switching to Serial Memory Mode to functionBence Csókás
SAMA7G5 support (that was forward-ported from v6.1) re-introduced a bug that was fixed in v6.12, thankfully only in the codepath of the new SoC. But to prevent similar mistakes in the future, we split out the offending code to a function, and use this, fixed version everywhere. To facilitate this, support function `atmel_qspi_update_config()` also had to be moved upwards. For best viewing experience, use `--color-moved-ws="allow-indentation-change" --color-moved`. Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") Reported-by: Alexander Dahl <ada@thorsis.com> Closes: https://lore.kernel.org/linux-spi/20241218-appliance-jaws-90773405977a@thorsis.com/ Signed-off-by: Bence Csókás <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20241218151754.365519-1-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-16spi: atmel-quadspi: Add support for sama7g5 QSPITudor Ambarus
The sama7g5 QSPI controller uses dedicated clocks for the QSPI Controller Interface and the QSPI Controller Core, and requires synchronization before accessing registers or bit fields. QSPI_SR.SYNCBSY must be zero before accessing any of the bits: QSPI_CR.QSPIEN, QSPI_CR.QSPIDIS, QSPI_CR.SRFRSH, QSPI_CR.SWRST, QSPI_CR.UPDCFG, QSPI_CR.STTFR, QSPI_CR.RTOUT, QSPI_CR.LASTXFER. Also, the QSPI controller core configuration can be updated by writing the QSPI_CR.UPDCFG bit to ‘1’. This is needed by the following registers: QSPI_MR, QSPI_SCR, QSPI_IAR, QSPI_WICR, QSPI_IFR, QSPI_RICR, QSPI_SMR, QSPI_SKR,QSPI_REFRESH, QSPI_WRACNT QSPI_PCALCFG. The Octal SPI supports frequencies up to 200 MHZ DDR. The need for output impedance calibration arises. To avoid the degradation of the signal quality, a PAD calibration cell is used to adjust the output impedance to the driven I/Os. The transmission flow requires different sequences for setting the configuration and for the actual transfer, than what is in the sama5d2 and sam9x60 versions of the IP. Different interrupts are handled. aq->ops->set_cfg() and aq->ops->transfer() are introduced to help differentiating the flows. Tested single and octal SPI mode with mx66lm1g45g. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20211214133404.121739-1-tudor.ambarus@microchip.com [varshini.rajendran@microchip.com: Fixed conflicts and ported to 6.1.4] Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> [ csokas.bence: Forward-port to master and address feedback ] Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20241128174316.3209354-3-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2024-12-16spi: atmel-quadspi: Create `atmel_qspi_ops` to support newer SoC familiesCsókás, Bence
Refactor the code to introduce an ops struct, to prepare for merging support for later SoCs, such as SAMA7G5. This code was based on the vendor's kernel (linux4microchip). Cc'ing original contributors. Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu> Link: https://patch.msgid.link/20241128174316.3209354-2-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2024-11-26spi: atmel-quadspi: Fix register name in verbose logging functionCsókás, Bence
`atmel_qspi_reg_name()` is used for pretty-printing register offsets for verbose logging of register accesses. However, due to a typo (likely a copy-paste error), QSPI_RD's offset prints as "MR", the name of the previous register. Fix this typo. Fixes: c528ecfbef04 ("spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses") Signed-off-by: Csókás, Bence <csokas.bence@prolan.hu> Reviewed-by: Alexander Dahl <ada@thorsis.com> Link: https://patch.msgid.link/20241122141302.2599636-1-csokas.bence@prolan.hu Signed-off-by: Mark Brown <broonie@kernel.org>
2024-10-07spi: Merge up v6.12Mark Brown
Fixes build issues with the KVM selftests.
2024-10-01spi: atmel-quadspi: Fix wrong register value written to MRAlexander Dahl
aq->mr should go to MR, nothing else. Fixes: 329ca3eed4a9 ("spi: atmel-quadspi: Avoid overwriting delay register settings") Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://lore.kernel.org/linux-spi/20240926-macarena-wincing-7c4995487a29@thorsis.com/T/#u Link: https://patch.msgid.link/20240926090356.105789-1-ada@thorsis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: atmel-quadspi: Add cs_hold and cs_inactive setting supportAlexander Dahl
spi-cs-inactive-delay-ns in dts is cs_inactive in spi core, and it maps to DLYCS (Minimum Inactive QCS Delay) in QSPI Mode Register (QSPI_MR). spi-cs-hold-delay-ns in dts is cs_hold in spi core, and it maps to DLYBCT (Delay Between Consecutive Transfers) in QSPI_MR. That one can be set to other values than 0 only if the chip is not in Serial Memory Mode (SMM), it must be written to '0' however when in SMM. Tested on SAM9X60 based board with FPGA implementing custom SPI Memory protocol. Signed-off-by: Alexander Dahl <ada@thorsis.com> Link: https://patch.msgid.link/20240918082744.379610-3-ada@thorsis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-30spi: Switch back to struct platform_driver::remove()Uwe Kleine-König
After commit 0edb555a65d1 ("platform: Make platform_driver::remove() return void") .remove() is (again) the right callback to implement for platform drivers. Convert all platform drivers below drivers/spi to use .remove(), with the eventual goal to drop struct platform_driver::remove_new(). As .remove() and .remove_new() have the same prototypes, conversion is done by just changing the structure member name in the driver initializer. The change for the spi-npcm-fiu stands out in the diffstat because the inconsistent formatting style of the platform_driver initializer is fixed to match the other struct initializer in the file. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://patch.msgid.link/20240925113501.25208-2-u.kleine-koenig@baylibre.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-20spi: atmel-quadspi: Avoid overwriting delay register settingsAlexander Dahl
Previously the MR and SCR registers were just set with the supposedly required values, from cached register values (cached reg content initialized to zero). All parts fixed here did not consider the current register (cache) content, which would make future support of cs_setup, cs_hold, and cs_inactive impossible. Setting SCBR in atmel_qspi_setup() erases a possible DLYBS setting from atmel_qspi_set_cs_timing(). The DLYBS setting is applied by ORing over the current setting, without resetting the bits first. All writes to MR did not consider possible settings of DLYCS and DLYBCT. Signed-off-by: Alexander Dahl <ada@thorsis.com> Fixes: f732646d0ccd ("spi: atmel-quadspi: Add support for configuring CS timing") Link: https://patch.msgid.link/20240918082744.379610-2-ada@thorsis.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-09-19spi: atmel-quadspi: Undo runtime PM changes at driver exit timeJinjie Ruan
It's important to undo pm_runtime_use_autosuspend() with pm_runtime_dont_use_autosuspend() at driver exit time unless driver initially enabled pm_runtime with devm_pm_runtime_enable() (which handles it for you). Hence, call pm_runtime_dont_use_autosuspend() at driver exit time to fix it. Fixes: 4a2f83b7f780 ("spi: atmel-quadspi: add runtime pm support") Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Link: https://patch.msgid.link/20240906023956.1004440-1-ruanjinjie@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-08-28spi: atmel-quadspi: Simplify with dev_err_probe()Jinjie Ruan
Use the dev_err_probe() helper to simplify error handling during probe. This also handle scenario, when EDEFER is returned and useless error is printed. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Link: https://patch.msgid.link/20240826125913.3434305-3-ruanjinjie@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-08-28spi: atmel-quadspi: Fix uninitialized resJinjie Ruan
The second platform_get_resource_byname() can not be replaced with devm_platform_ioremap_resource_byname(), because the intermediate "res" is used to assign for "aq->mmap_size". Fixes: 3ccea1dedef3 ("spi: atmel-quadspi: Simpify resource lookup") Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Acked-by: Hari Prasath Gujulan Elango <hari.prasathge@microchip.com> Link: https://patch.msgid.link/20240826125913.3434305-2-ruanjinjie@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-08-23spi: atmel-quadspi: Simpify resource lookupJinjie Ruan
Use the devm_platform_ioremap_resource_byname() helper instead of calling platform_get_resource_byname() and devm_ioremap_resource() separately. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Link: https://patch.msgid.link/20240820123818.1788432-1-ruanjinjie@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2024-05-27spi: atmel-quadspi: Add missing check for clk_prepareChen Ni
Add check for the return value of clk_prepare() and return the error if it fails in order to catch the error. Fixes: 4a2f83b7f780 ("spi: atmel-quadspi: add runtime pm support") Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Link: https://msgid.link/r/20240515084028.3210406-1-nichen@iscas.ac.cn Signed-off-by: Mark Brown <broonie@kernel.org>
2023-11-30spi: Unify error codes by replacing -ENOTSUPP with -EOPNOTSUPPChia-Lin Kao (AceLan)
This commit updates the SPI subsystem, particularly affecting "SPI MEM" drivers and core parts, by replacing the -ENOTSUPP error code with -EOPNOTSUPP. The key motivations for this change are as follows: 1. The spi-nor driver currently uses EOPNOTSUPP, whereas calls to spi-mem might return ENOTSUPP. This update aims to unify the error reporting within the SPI subsystem for clarity and consistency. 2. The use of ENOTSUPP has been flagged by checkpatch as inappropriate, mainly being reserved for NFS-related errors. To align with kernel coding standards and recommendations, this change is being made. 3. By using EOPNOTSUPP, we provide more specific context to the error, indicating that a particular operation is not supported. This helps differentiate from the more generic ENOTSUPP error, allowing drivers to better handle and respond to different error scenarios. Risks and Considerations: While this change is primarily intended as a code cleanup and error code unification, there is a minor risk of breaking user-space applications that rely on specific return codes for unsupported operations. However, this risk is considered low, as such use-cases are unlikely to be common or critical. Nevertheless, developers and users should be aware of this change, especially if they have scripts or tools that specifically handle SPI error codes. This commit does not introduce any functional changes to the SPI subsystem or the affected drivers. Signed-off-by: "Chia-Lin Kao (AceLan)" <acelan.kao@canonical.com> Acked-by: Tudor Ambarus <tudor.ambarus@linaro.org> Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20231129064311.272422-1-acelan.kao@canonical.com Signed-off-by: Mark Brown <broonie@kernel.org>
2023-03-17spi: atmel-quadspi: Convert to platform remove callback returning voidUwe Kleine-König
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is (mostly) ignored and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20230317084232.142257-4-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2023-03-17spi: atmel-quadspi: Free resources even if runtime resume failed in .remove()Uwe Kleine-König
An early error exit in atmel_qspi_remove() doesn't prevent the device unbind. So this results in an spi controller with an unbound parent and unmapped register space (because devm_ioremap_resource() is undone). So using the remaining spi controller probably results in an oops. Instead unregister the controller unconditionally and only skip hardware access and clk disable. Also add a warning about resume failing and return zero unconditionally. The latter has the only effect to suppress a less helpful error message by the spi core. Fixes: 4a2f83b7f780 ("spi: atmel-quadspi: add runtime pm support") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20230317084232.142257-3-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2023-03-17spi: atmel-quadspi: Don't leak clk enable count in pm resumeUwe Kleine-König
The pm resume call is supposed to enable two clocks. If the second enable fails the callback reports failure but doesn't undo the first enable. So call clk_disable() for the first clock when clk_enable() for the second one fails. Fixes: 4a2f83b7f780 ("spi: atmel-quadspi: add runtime pm support") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20230317084232.142257-2-u.kleine-koenig@pengutronix.de Signed-off-by: Mark Brown <broonie@kernel.org>
2023-01-23spi: atmel-quadspi: switch to use modern nameYang Yingliang
Change legacy name master to modern name host or controller. No functional changed. Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20230110131805.2827248-4-yangyingliang@huawei.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-11-18spi: atmel-quadspi: Add support for configuring CS timingTudor Ambarus
The at91 QSPI IP uses a default value of half of the period of the QSPI clock period for the cs-setup time, which is not always enough, an example being the sst26vf064b SPI NOR flash which requires a minimum cs-setup time of 5 ns. It was observed that none of the at91 SoCs can fulfill the minimum CS setup time for the aforementioned flash, as they operate at high frequencies and half a period does not suffice for the required CS setup time. Add support for configuring the CS timing in the controller. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20221117105249.115649-5-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-09spi: atmel-quadspi: align condition to parenthesisClaudiu Beznea
Align condition to parenthesis. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609084246.1795419-4-claudiu.beznea@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-09spi: atmel-quadspi: use pm_ptr()Claudiu Beznea
Use pm_ptr() for atmel_quadspi_pm_ops. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609084246.1795419-3-claudiu.beznea@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-06-09spi: atmel-quadspi: add runtime pm supportClaudiu Beznea
Add runtime PM support for atmel-quadspi which will disable/enable QSPI clocks on proper runtime_suspend/runtime_resume ops. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Link: https://lore.kernel.org/r/20220609084246.1795419-2-claudiu.beznea@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-13spi: atmel-quadspi: Remove duplicated DTR checksTudor Ambarus
Remove the DTR checks as they are already handled in spi_mem_default_supports_op(). This code removal was intentionally not done in the previous patch that introduced the use of the spi_mem_default_supports_op() core helper and fixed the buswidth adjustment between SPIMEM and the SPI controller, so that the fix can be easily backported to stable kernels. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220406133604.455356-2-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2022-04-13spi: atmel-quadspi: Fix the buswidth adjustment between spi-mem and controllerTudor Ambarus
Use the spi_mem_default_supports_op() core helper in order to take into account the buswidth specified by the user in device tree. Cc: <stable@vger.kernel.org> Fixes: 0e6aae08e9ae ("spi: Add QuadSPI driver for Atmel SAMA5D2") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20220406133604.455356-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-09-20spi: Fixed division by zero warningYoshitaka Ikeda
The reason for dividing by zero is because the dummy bus width is zero, but if the dummy n bytes is zero, it indicates that there is no data transfer, so there is no need for calculation. Fixes: 7512eaf54190 ("spi: cadence-quadspi: Fix dummy cycle calculation when buswidth > 1") Signed-off-by: Yoshitaka Ikeda <ikeda@nskint.co.jp> Acked-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/OSZPR01MB70049C8F56ED8902852DF97B8BD49@OSZPR01MB7004.jpnprd01.prod.outlook.com Signed-off-by: Mark Brown <broonie@kernel.org>
2021-02-11spi: atmel-quadspi: Disable the QSPI IP at suspend()Tudor Ambarus
It is safer to disable the QSPI IP at suspend, in order to avoid possible impact of glitches on the internal FSMs. This is a theoretical fix, there were no problems seen as of now. Tested on sama5d2 and sam9x60 versions of the IP. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20210210135428.204134-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-12-07Merge series "spi: atmel-quadspi: Fix AHB memory accesses" from Tudor ↵Mark Brown
Ambarus <tudor.ambarus@microchip.com>: Starting with the move of the atmel-quadspi driver under SPI, the following error could be seen when mounting a 16MByte ubifs: UBIFS error (ubi0:0 pid 1893): check_lpt_type.constprop.6: invalid type (15) in LPT node type 1/4 fixes AHB accesses. The rest of the patches are small optimizations. Tested on both sama5d2 and sam9x60. Tudor Ambarus (4): spi: atmel-quadspi: Fix AHB memory accesses spi: atmel-quadspi: Drop superfluous set of QSPI_IFR_APBTFRTYP_READ spi: atmel-quadspi: Write QSPI_IAR only when needed spi: atmel-quadspi: Move common code outside of if else drivers/spi/atmel-quadspi.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) -- 2.25.1 base-commit: 3650b228f83adda7e5ee532e2b90429c03f7b9ec _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
2020-12-07spi: atmel-quadspi: Fix use-after-free on unbindLukas Wunner
atmel_qspi_remove() accesses the driver's private data after calling spi_unregister_controller() even though that function releases the last reference on the spi_controller and thereby frees the private data. Fix by switching over to the new devm_spi_alloc_master() helper which keeps the private data accessible until the driver has unbound. Fixes: 2d30ac5ed633 ("mtd: spi-nor: atmel-quadspi: Use spi-mem interface for atmel-quadspi driver") Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: <stable@vger.kernel.org> # v5.0+: 5e844cc37a5c: spi: Introduce device-managed SPI controller allocation Cc: <stable@vger.kernel.org> # v5.0+ Cc: Piotr Bugalski <bugalski.piotr@gmail.com> Link: https://lore.kernel.org/r/4b05c65cf6f1ea3251484fe9a00b4c65478a1ae3.1607286887.git.lukas@wunner.de Signed-off-by: Mark Brown <broonie@kernel.org>
2020-12-07spi: atmel-quadspi: Move common code outside of if elseTudor Ambarus
QSPI_IFR is set as the last QSPI Instruction Frame register regardless of the sama5d2 or sam9x60 version of the IP. Move the writing of QSPI_IFR outside of the IP specific code. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20201207135959.154124-5-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-12-07spi: atmel-quadspi: Write QSPI_IAR only when neededTudor Ambarus
The address must be written in QSPI_IAR only when we have a instruction frame with address but no data. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20201207135959.154124-4-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-12-07spi: atmel-quadspi: Drop superfluous set of QSPI_IFR_APBTFRTYP_READTudor Ambarus
That bit describes the APB transfer type. We are writing serial memory registers via AHB acesses, that bit does not make sense in the current context. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20201207135959.154124-3-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-12-07spi: atmel-quadspi: Fix AHB memory accessesTudor Ambarus
Following error was seen when mounting a 16MByte ubifs: UBIFS error (ubi0:0 pid 1893): check_lpt_type.constprop.6: invalid type (15) in LPT node type QSPI_IFR.TFRTYP was not set correctly. When data transfer is enabled and one wants to access the serial memory through AHB in order to: - read in the serial memory, but not a memory data, for example a JEDEC-ID, QSPI_IFR.TFRTYP must be written to '0' (both sama5d2 and sam9x60). - read in the serial memory, and particularly a memory data, TFRTYP must be written to '1' (both sama5d2 and sam9x60). - write in the serial memory, but not a memory data, for example writing the configuration or the QSPI_SR, TFRTYP must be written to '2' for sama5d2 and to '0' for sam9x60. - write in the serial memory in particular to program a memory data, TFRTYP must be written to '3' for sama5d2 and to '1' for sam9x60. Fix the setting of the QSPI_IFR.TFRTYP field. Fixes: 2d30ac5ed633 ("mtd: spi-nor: atmel-quadspi: Use spi-mem interface for atmel-quadspi driver") Cc: <stable@vger.kernel.org> # v5.0+ Reported-by: Tom Burkart <tom@aussec.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20201207135959.154124-2-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-11-10spi: atmel-quadspi: Disable clock in probe error pathLukas Wunner
If the call to of_device_get_match_data() fails on probe of the Atmel QuadSPI driver, the clock "aq->pclk" is erroneously not unprepared and disabled. Fix it. Fixes: 2e5c88887358 ("spi: atmel-quadspi: add support for sam9x60 qspi controller") Signed-off-by: Lukas Wunner <lukas@wunner.de> Cc: <stable@vger.kernel.org> # v5.1+ Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/8f8dc2815aa97b2378528f08f923bf81e19611f0.1604874488.git.lukas@wunner.de Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-17spi: atmel-quadspi: Use optimezed memcpy_fromio()/memcpy_toio()Tudor Ambarus
Optimezed mem*io operations are defined for LE platforms, use them. The ARM and !ARCH_EBSA110 dependencies for COMPILE_TEST were added only for the _memcpy_fromio()/_memcpy_toio() functions. Drop these dependencies. Tested unaligned accesses on both sama5d2 and sam9x60 QSPI controllers using SPI NOR flashes, everything works ok. The following performance improvement can be seen when running mtd_speedtest: sama5d2_xplained (mx25l25635e) - before: mtd_speedtest: eraseblock write speed is 983 KiB/s mtd_speedtest: eraseblock read speed is 6150 KiB/s - after: mtd_speedtest: eraseblock write speed is 1055 KiB/s mtd_speedtest: eraseblock read speed is 20144 KiB/s sam9x60ek (sst26vf064b) - before: mtd_speedtest: eraseblock write speed is 4770 KiB/s mtd_speedtest: eraseblock read speed is 8062 KiB/s - after: mtd_speedtest: eraseblock write speed is 4524 KiB/s mtd_speedtest: eraseblock read speed is 21186 KiB/s Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200716043139.565734-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-14spi: atmel-quadspi: reject DTR opsPratyush Yadav
Double Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op(). Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200623183030.26591-4-p.yadav@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-03-20spi: atmel-quadspi: Add verbose debug facilities to monitor register accessesTudor Ambarus
This feature should not be enabled in release but can be useful for developers who need to monitor register accesses at some specific places. Helped me identify a bug in u-boot, by comparing the register accesses from the linux driver with the ones from its u-boot variant. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200320065058.891221-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2020-02-28spi: atmel-quadspi: fix possible MMIO window size overrunTudor Ambarus
The QSPI controller memory space is limited to 128MB: 0x9000_00000-0x9800_00000/0XD000_0000--0XD800_0000. There are nor flashes that are bigger in size than the memory size supported by the controller: Micron MT25QL02G (256 MB). Check if the address exceeds the MMIO window size. An improvement would be to add support for regular SPI mode and fall back to it when the flash memories overrun the controller's memory space. Fixes: 0e6aae08e9ae ("spi: Add QuadSPI driver for Atmel SAMA5D2") Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200228155437.1558219-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>
2019-08-02spi: Remove dev_err() usage after platform_get_irq()Stephen Boyd
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Mark Brown <broonie@kernel.org> Cc: linux-spi@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Boyd <swboyd@chromium.org> Link: https://lore.kernel.org/r/20190730181557.90391-42-swboyd@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-02spi: atmel-quadspi: fix resume callTudor Ambarus
When waking up from the Suspend-to-RAM state, the following error was seen: m25p80 spi2.0: flash operation timed out The flash remained in an undefined state, returning 0xFFs. Fix it by setting the Serial Clock Baud Rate, as it was set before the conversion to SPIMEM. Tested with sama5d2_xplained and mx25l25673g spi-nor in Backup + Self-Refresh and Suspend modes. Fixes: 0e6aae08e9ae ("spi: Add QuadSPI driver for Atmel SAMA5D2") Reported-by: Mark Deneen <mdeneen@gmail.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-07-02spi: atmel-quadspi: void return type for atmel_qspi_init()Tudor Ambarus
commit 2d30ac5ed633 ("mtd: spi-nor: atmel-quadspi: Use spi-mem interface for atmel-quadspi driver") removed the error path from atmel_qspi_init(), but not changed the function's return type. Set void return type for atmel_qspi_init(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-05-02Merge branch 'spi-5.2' into spi-nextMark Brown
2019-05-02spi: atmel-quadspi: fix crash while suspendingClaudiu Beznea
atmel_qspi objects are kept in spi_controller objects, so, first get pointer to spi_controller object and then get atmel_qspi object from spi_controller object. Fixes: 2d30ac5ed633 ("mtd: spi-nor: atmel-quadspi: Use spi-mem interface for atmel-quadspi driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-03-25spi: atmel-quadspi: Make atmel_qspi_get_name staticYueHaibing
Fix sparse warning: drivers/spi/atmel-quadspi.c:369:12: warning: symbol 'atmel_qspi_get_name' was not declared. Should it be static? Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Mark Brown <broonie@kernel.org>
2019-02-06spi: atmel-quadspi: add support for sam9x60 qspi controllerTudor Ambarus
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register access, the other for the qspi core and phy. Both are mandatory. It uses different transfer type bits in IFR register. It has dedicated registers to specify a read or a write instruction: Read Instruction Code Register (RICR) and Write Instruction Code Register (WICR). ICR/RICR/WICR have identical fields. Tested with sst26vf064b jedec,spi-nor flash. Backward compatibility test done on sama5d2 qspi controller and mx25l25635e jedec,spi-nor flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Mark Brown <broonie@kernel.org>