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path: root/drivers/gpu/drm/i915
AgeCommit message (Expand)Author
2021-02-17drm/i915/gt: Correct surface base address for renderclearChris Wilson
2021-02-17drm/i915: Disallow plane x+w>stride on ilk+ with X-tilingVille Syrjälä
2021-02-08drm/i915: Reject 446-480MHz HDMI clock on GLKVille Syrjälä
2021-02-08drm/i915/gt: Flush before changing register stateChris Wilson
2021-02-08drm/i915: Disable atomics in L3 for gen9Chris Wilson
2021-02-08drm/i915/gem: Move freeze/freeze_late next to suspend/suspend_lateChris Wilson
2021-02-08drm/i915/gem: Fix oops in error handling codeDan Carpenter
2021-02-08drm/i915/gvt: fix uninitialized return in intel_gvt_update_reg_whitelist()Dan Carpenter
2021-02-08drm/i915: Restrict DRM_I915_DEBUG to developer buildsChris Wilson
2021-02-04Merge tag 'drm-intel-next-2021-01-29' of git://anongit.freedesktop.org/drm/dr...Dave Airlie
2021-01-29drm/i915/dp: Prevent setting the LTTPR LT mode if no LTTPRs are detectedImre Deak
2021-01-29drm/i915: Implement async flips for vlv/chvVille Syrjälä
2021-01-29drm/i915: Implement async flip for ilk/snbVille Syrjälä
2021-01-29drm/i915: Implement async flip for ivb/hswVille Syrjälä
2021-01-29drm/i915: Implement async flips for bdwVille Syrjälä
2021-01-29drm/i915: Limit plane stride to below TILEOFF.x limitVille Syrjälä
2021-01-29drm/i915: Rename is_16gb_dimm to wm_lv_0_adjust_neededJosé Roberto de Souza
2021-01-29drm/i915/gen11+: Only load DRAM information from pcodeJosé Roberto de Souza
2021-01-29drm/i915: Nuke not needed members of dram_infoJosé Roberto de Souza
2021-01-29Merge tag 'drm-intel-next-2021-01-27' of git://anongit.freedesktop.org/drm/dr...Dave Airlie
2021-01-28drm/i915: Fix the MST PBN divider calculationImre Deak
2021-01-28drm/i915/hdcp: Disable the QSES check for HDCP 1.4 over MSTSean Paul
2021-01-28drm/i915/display: Prevent double YUV range correction on HDR planesAndres Calderon Jaramillo
2021-01-27drm/i915: WARN if plane src coords are too bigVille Syrjälä
2021-01-26drm/i915/display/vrr: Skip the VRR HW state readout on DSI transcoderManasi Navare
2021-01-26drm/i915: Do a bit more initial readout for dbufVille Syrjälä
2021-01-26drm/i915: Encapsulate dbuf state handling harderVille Syrjälä
2021-01-26drm/i915: Extract intel_crtc_dbuf_weights()Ville Syrjälä
2021-01-26drm/i915: Add pipe ddb entries into the dbuf stateVille Syrjälä
2021-01-26drm/i915: Introduce skl_ddb_entry_for_slices()Ville Syrjälä
2021-01-26drm/i915: Introduce intel_dbuf_slice_size()Ville Syrjälä
2021-01-26drm/i915: Pass the crtc to skl_compute_dbuf_slices()Ville Syrjälä
2021-01-26drm/i915: Extract intel_crtc_ddb_weight()Ville Syrjälä
2021-01-25drm/i915: Fix vblank evasion with vrrVille Syrjälä
2021-01-25drm/i915: Fix vblank timestamps with VRRVille Syrjälä
2021-01-25drm/i915: Add vrr state dumpVille Syrjälä
2021-01-25drm/i915/display: Helpers for VRR vblank min and max startVille Syrjälä
2021-01-25drm/i915/display: Add HW state readout for VRRManasi Navare
2021-01-25drm/i915/display/vrr: Set IGNORE_MSA_PAR state in DP SinkManasi Navare
2021-01-25drm/i915/display/vrr: Disable VRR in modeset disable pathManasi Navare
2021-01-25drm/i915/display/vrr: Send VRR push to flip the frameManasi Navare
2021-01-25drm/i915/display/vrr: Configure and enable VRR in modeset enableManasi Navare
2021-01-25drm/i915: Rename VRR_CTL reg fieldsVille Syrjälä
2021-01-25drm/i915/display: VRR + DRRS cannot be enabled togetherVille Syrjälä
2021-01-25drm/i915/display/dp: Do not enable PSR if VRR is enabledManasi Navare
2021-01-25drm/i915/display/dp: Compute VRR state in atomic_checkManasi Navare
2021-01-25drm/i915: Extract intel_crtc_scanlines_since_frame_timestamp()Ville Syrjälä
2021-01-25drm/i915: Extract intel_mode_vblank_start()Ville Syrjälä
2021-01-25drm/i915: Store framestart_delay in dev_privVille Syrjälä
2021-01-25drm/i915/display/dp: Attach and set drm connector VRR propertyAditya Swarup