lwn.git - Linux kernel documentation tree maintained by Jonathan Corbet

Age	Commit message (Expand)	Author
2021-12-15	clk: tegra: Support runtime PM and power domain	Dmitry Osipenko
2021-05-31	clk: tegra: Don't deassert reset on enabling clocks	Dmitry Osipenko
2021-01-05	memory: tegra124-emc: Make driver modular	Dmitry Osipenko
2020-05-12	clk: tegra: cclk: Add helpers for handling PLLX rate changes	Dmitry Osipenko
2020-05-12	clk: tegra: pll: Add pre/post rate-change hooks	Dmitry Osipenko
2020-05-12	clk: tegra: Add custom CCLK implementation	Dmitry Osipenko
2020-05-12	clk: tegra: Implement Tegra210 EMC clock	Joseph Lo
2020-05-12	clk: tegra: Rename Tegra124 EMC clock source file	Thierry Reding
2020-03-12	clk: tegra: Remove tegra_pmc_clk_init along with clk ids	Sowjanya Komatineni
2019-11-11	clk: tegra: Add suspend and resume support on Tegra210	Sowjanya Komatineni
2019-11-11	clk: tegra: Share clk and rst register defines with Tegra clock driver	Sowjanya Komatineni
2019-11-11	clk: tegra: clk-super: Fix to enable PLLP branches to CPU	Sowjanya Komatineni
2019-11-11	clk: tegra: Support for OSC context save and restore	Sowjanya Komatineni
2019-11-11	clk: tegra: Add Tegra20/30 EMC clock implementation	Dmitry Osipenko
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	Thomas Gleixner
2018-12-14	clk: tegra: Fix maximum audio sync clock for Tegra124/210	Jon Hunter
2018-07-25	clk: tegra: Add sdmmc mux divider clock	Peter De-Schrijver
2018-07-25	clk: tegra: Refactor fractional divider calculation	Peter De Schrijver
2018-07-25	clk: tegra: Fix includes required by fence_udelay()	Aapo Vienamo
2018-05-18	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	Dmitry Osipenko
2018-03-08	clk: tegra: add fence_delay for clock registers	Peter De Schrijver
2017-10-19	clk: tegra: Add peripheral clock registration helper	Thierry Reding
2017-08-23	clk: tegra: Re-factor T210 PLLX registration	Alex Frid
2017-03-20	clk: tegra: Fix build warnings on Tegra20/Tegra30	Thierry Reding
2017-03-20	clk: tegra: Add super clock mux/divider	Peter De Schrijver
2017-03-20	clk: tegra: Fix constness for peripheral clocks	Peter De Schrijver
2017-03-20	clk: tegra: Fix type for m field	Peter De Schrijver
2016-06-30	clk: tegra: Initialize UTMI PLL when enabling PLLU	Andrew Bresticker
2016-04-28	clk: tegra: Fix pllre Tegra210 and add pll_re_out1	Rhyland Klein
2016-04-28	clk: tegra: Add fixed factor peripheral clock type	Thierry Reding
2016-04-28	clk: tegra: Constify peripheral clock registers	Thierry Reding
2015-12-17	clk: tegra: Add support for Tegra210 clocks	Rhyland Klein
2015-12-17	clk: tegra: Add Super Gen5 Logic	Bill Huang
2015-12-17	clk: tegra: pll: Add logic for SS	Bill Huang
2015-12-17	clk: tegra: pll: Add dyn_ramp callback	Rhyland Klein
2015-12-17	clk: tegra: pll: Add Set_default logic	Bill Huang
2015-12-17	clk: tegra: pll: Adjust vco_min if SDM present	Bill Huang
2015-12-17	clk: tegra: pll: Add support for PLLMB for Tegra210	Rhyland Klein
2015-12-17	clk: tegra: pll: Add specialized logic for Tegra210	Rhyland Klein
2015-11-20	clk: tegra: pll: Add code to handle if resets are supported by PLL	Bill Huang
2015-11-20	clk: tegra: pll: Add logic for out-of-table rates for T210	Rhyland Klein
2015-11-20	clk: tegra: pll: Add logic for handling SDM data	Rhyland Klein
2015-11-20	clk: tegra: pll: Change misc_reg count from 3 to 6	Bill Huang
2015-11-20	clk: tegra: pll: Add tegra_pll_wait_for_lock to clk header	Rhyland Klein
2015-11-20	clk: tegra: Constify pdiv-to-hw mappings	Thierry Reding
2015-10-20	clk: tegra: Modify tegra_audio_clk_init to accept more plls	Rhyland Klein
2015-10-20	clk: tegra: Update struct tegra_clk_pll_params kerneldoc	Thierry Reding
2015-10-20	clk: tegra: Fix comments for structure definitions	Rhyland Klein
2015-07-16	clk: tegra: Introduce ability for SoC-specific reset control callbacks	Mikko Perttunen
2015-05-13	clk: tegra: EMC clock driver depends on EMC driver	Thierry Reding