Age | Commit message (Expand) | Author |
---|---|---|
2022-06-10 | treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (pa... | Thomas Gleixner |
2015-07-17 | Update Viresh Kumar's email address | Viresh Kumar |
2012-11-21 | CLK: SPEAr: Correct index scanning done for clock synths | Deepak Sikri |
2012-06-20 | Viresh has moved | Viresh Kumar |
2012-05-12 | SPEAr: clk: Add VCO-PLL Synthesizer clock | Viresh Kumar |