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path: root/arch/riscv/kernel/fpu.S
AgeCommit message (Expand)Author
2024-10-18RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNEDJesse Taube
2024-05-22riscv: typo in comment for get_f64_regXingyou Chen
2023-11-06riscv: Use SYM_*() assembly macros instead of deprecated onesClément Léger
2023-11-01riscv: add floating point insn support to misaligned access emulationClément Léger
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng
2018-10-22Extract FPU context operations from entry.SAlan Kao