| Age | Commit message (Expand) | Author |
|---|
| 2024-10-18 | RISC-V: Replace RISCV_MISALIGNED with RISCV_SCALAR_MISALIGNED | Jesse Taube |
| 2024-05-22 | riscv: typo in comment for get_f64_reg | Xingyou Chen |
| 2023-11-06 | riscv: Use SYM_*() assembly macros instead of deprecated ones | Clément Léger |
| 2023-11-01 | riscv: add floating point insn support to misaligned access emulation | Clément Léger |
| 2019-11-05 | riscv: abstract out CSR names for supervisor vs machine mode | Christoph Hellwig |
| 2019-08-30 | riscv: Using CSR numbers to access CSRs | Bin Meng |
| 2018-10-22 | Extract FPU context operations from entry.S | Alan Kao |
