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memory-region 0: Reserved trace buffer memory
TMC ETR: When available, use this reserved memory region for
trace data capture. Same region is used for trace data
retention after a panic or watchdog reset.
TMC ETF: When available, use this reserved memory region for
trace data retention synced from internal SRAM after a panic or
watchdog reset.
memory-region 1: Reserved meta data memory
TMC ETR, ETF: When available, use this memory for register
snapshot retention synced from hardware registers after a panic
or watchdog reset.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linu Cherian <lcherian@marvell.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250212114918.548431-2-lcherian@marvell.com
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The Coresight TMC component may be behind an IOMMU which is the case for
the Arm Juno SoC and some Qualcomm SoCs. Add 'iommus' property to the
binding.
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220721212718.1980905-2-robh@kernel.org
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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Coresight components may be in a power domain which is the case for the Arm
Juno board. Allow a single 'power-domains' entry for Coresight components.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Sudeep Holla <sudeep.holla@arm.com>
Link: https://lore.kernel.org/r/20220721212718.1980905-1-robh@kernel.org
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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Each CoreSight component has slightly different requirements and
nothing applies to every component, so each CoreSight component has its
own schema document.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20220603011933.3277315-3-robh@kernel.org
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
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