diff options
Diffstat (limited to 'drivers/iio/adc/meson_saradc.c')
| -rw-r--r-- | drivers/iio/adc/meson_saradc.c | 47 |
1 files changed, 17 insertions, 30 deletions
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c index 2d475b43e717..997def4a4d2f 100644 --- a/drivers/iio/adc/meson_saradc.c +++ b/drivers/iio/adc/meson_saradc.c @@ -155,10 +155,10 @@ */ #define MESON_SAR_ADC_REG11 0x2c #define MESON_SAR_ADC_REG11_BANDGAP_EN BIT(13) - #define MESON_SAR_ADC_REG11_CMV_SEL BIT(6) - #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5) - #define MESON_SAR_ADC_REG11_EOC BIT(1) - #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0) + #define MESON_SAR_ADC_REG11_CMV_SEL BIT(6) + #define MESON_SAR_ADC_REG11_VREF_VOLTAGE BIT(5) + #define MESON_SAR_ADC_REG11_EOC BIT(1) + #define MESON_SAR_ADC_REG11_VREF_SEL BIT(0) #define MESON_SAR_ADC_REG13 0x34 #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK GENMASK(13, 8) @@ -315,19 +315,17 @@ static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = { struct meson_sar_adc_param { bool has_bl30_integration; unsigned long clock_rate; - u32 bandgap_reg; unsigned int resolution; const struct regmap_config *regmap_config; u8 temperature_trimming_bits; unsigned int temperature_multiplier; unsigned int temperature_divider; u8 disable_ring_counter; - bool has_reg11; bool has_vref_select; u8 vref_select; u8 cmv_select; u8 adc_eoc; - enum meson_sar_adc_vref_sel vref_volatge; + enum meson_sar_adc_vref_sel vref_voltage; }; struct meson_sar_adc_data { @@ -976,7 +974,7 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN, regval); - if (priv->param->has_reg11) { + if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) { regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc); regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, MESON_SAR_ADC_REG11_EOC, regval); @@ -989,7 +987,7 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) } regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE, - priv->param->vref_volatge); + priv->param->vref_voltage); regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval); @@ -1013,16 +1011,15 @@ static int meson_sar_adc_init(struct iio_dev *indio_dev) static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off) { struct meson_sar_adc_priv *priv = iio_priv(indio_dev); - const struct meson_sar_adc_param *param = priv->param; - u32 enable_mask; - if (param->bandgap_reg == MESON_SAR_ADC_REG11) - enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN; + if (priv->param->regmap_config->max_register >= MESON_SAR_ADC_REG11) + regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11, + MESON_SAR_ADC_REG11_BANDGAP_EN, + on_off ? MESON_SAR_ADC_REG11_BANDGAP_EN : 0); else - enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN; - - regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask, - on_off ? enable_mask : 0); + regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, + MESON_SAR_ADC_DELTA_10_TS_VBG_EN, + on_off ? MESON_SAR_ADC_DELTA_10_TS_VBG_EN : 0); } static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev) @@ -1186,7 +1183,6 @@ static const struct iio_info meson_sar_adc_iio_info = { static const struct meson_sar_adc_param meson_sar_adc_meson8_param = { .has_bl30_integration = false, .clock_rate = 1150000, - .bandgap_reg = MESON_SAR_ADC_DELTA_10, .regmap_config = &meson_sar_adc_regmap_config_meson8, .resolution = 10, .temperature_trimming_bits = 4, @@ -1197,7 +1193,6 @@ static const struct meson_sar_adc_param meson_sar_adc_meson8_param = { static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = { .has_bl30_integration = false, .clock_rate = 1150000, - .bandgap_reg = MESON_SAR_ADC_DELTA_10, .regmap_config = &meson_sar_adc_regmap_config_meson8, .resolution = 10, .temperature_trimming_bits = 5, @@ -1208,35 +1203,29 @@ static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = { static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = { .has_bl30_integration = true, .clock_rate = 1200000, - .bandgap_reg = MESON_SAR_ADC_REG11, .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 10, - .has_reg11 = true, - .vref_volatge = 1, + .vref_voltage = 1, .cmv_select = 1, }; static const struct meson_sar_adc_param meson_sar_adc_gxl_param = { .has_bl30_integration = true, .clock_rate = 1200000, - .bandgap_reg = MESON_SAR_ADC_REG11, .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 12, .disable_ring_counter = 1, - .has_reg11 = true, - .vref_volatge = 1, + .vref_voltage = 1, .cmv_select = 1, }; static const struct meson_sar_adc_param meson_sar_adc_axg_param = { .has_bl30_integration = true, .clock_rate = 1200000, - .bandgap_reg = MESON_SAR_ADC_REG11, .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 12, .disable_ring_counter = 1, - .has_reg11 = true, - .vref_volatge = 1, + .vref_voltage = 1, .has_vref_select = true, .vref_select = VREF_VDDA, .cmv_select = 1, @@ -1245,11 +1234,9 @@ static const struct meson_sar_adc_param meson_sar_adc_axg_param = { static const struct meson_sar_adc_param meson_sar_adc_g12a_param = { .has_bl30_integration = false, .clock_rate = 1200000, - .bandgap_reg = MESON_SAR_ADC_REG11, .regmap_config = &meson_sar_adc_regmap_config_gxbb, .resolution = 12, .disable_ring_counter = 1, - .has_reg11 = true, .adc_eoc = 1, .has_vref_select = true, .vref_select = VREF_VDDA, |