ALL_CRTCS, &adp_plane_funcs,

plane_formats, ARRAY_SIZE(plane_formats),

NULL, DRM_PLANE_TYPE_PRIMARY, "plane");

drm_err(drm, "failed to allocate plane");

}

drm_plane_helper_add(plane, &adp_plane_helper_funcs);

AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,

AMDGPU_CP_KIQ_IRQ_LAST

};

#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */

#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */

#define MAX_KIQ_REG_TRY 1000

{

const struct aca_bank_ops *bank_ops = handle->bank_ops;

if (!aca_bank_hwip_is_matched(bank, handle->hwip))

return false;

(ACA_REG__STATUS__POISON((bank)->regs[ACA_REG_IDX_STATUS]) || \

ACA_REG__STATUS__DEFERRED((bank)->regs[ACA_REG_IDX_STATUS]))

enum aca_reg_idx {

ACA_REG_IDX_CTL = 0,

ACA_REG_IDX_STATUS = 1,

return true;

}

static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev)

{

if (amdgpu_atrm_get_bios(adev)) {

goto success;

}

}

if (amdgpu_read_bios_from_rom(adev)) {

adev, adev->ip_blocks[i].version->type))

continue;

/* skip suspend of gfx/mes and psp for S0ix

* gfx is in gfxoff state, so on resume it will exit gfxoff just

* like at runtime. PSP is also part of the always on hardware

MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin");

MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin");

MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin");

#define mmIP_DISCOVERY_VERSION 0x16A00

#define mmRCC_CONFIG_MEMSIZE 0xde3

*/

static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)

{

}

/**

r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);

if (r)

return ERR_PTR(r);

}

switch (bo->tbo.resource->mem_type) {

struct sg_table *sgt,

enum dma_data_direction dir)

{

dma_unmap_sgtable(attach->dev, sgt, dir, 0);

sg_free_table(sgt);

kfree(sgt);

};

static const struct pci_device_id pciidlist[] = {

{0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},

{0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},

{0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},

{0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},

{0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},

{0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},

/* Kaveri */

{0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},

{0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},

{0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},

{0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},

{0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},

/* topaz */

{0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},

{0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},

return -ENOTSUPP;

}

#ifdef CONFIG_DRM_AMDGPU_SI

dev_info(&pdev->dev,

"SI support provided by radeon.\n");

dev_info(&pdev->dev,

);

return -ENODEV;

}

#endif

#ifdef CONFIG_DRM_AMDGPU_CIK

dev_info(&pdev->dev,

"CIK support provided by radeon.\n");

dev_info(&pdev->dev,

);

return -ENODEV;

}

#endif

adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);

if (IS_ERR(adev))

} while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);

seq != ring->fence_drv.sync_seq)

amdgpu_fence_schedule_fallback(ring);

amdgpu_irq_put(adev, ring->fence_drv.irq_src,

ring->fence_drv.irq_type);

}

}

uint32_t flush_type, bool all_hub,

uint32_t inst)

{

struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;

struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];

unsigned int ndw;

uint32_t seq;

/*

amdgpu_ring_commit(ring);

spin_unlock(&adev->gfx.kiq[inst].ring_lock);

dev_err(adev->dev, "timeout waiting for kiq fence\n");

r = -ETIME;

}

error_unlock_reset:

return;

amdgpu_mes_remove_hw_queue(adev, ring->hw_queue_id);

amdgpu_ring_fini(ring);

kfree(ring);

}

* When GTT is just an alternative to VRAM make sure that we

* only use it as fallback and still try to fill up VRAM first.

*/

places[c].flags |= TTM_PL_FLAG_FALLBACK;

c++;

}

"jpeg",

"ih",

"mpio",

};

const char *ras_mca_block_string[] = {

AMDGPU_RAS_BLOCK__JPEG,

AMDGPU_RAS_BLOCK__IH,

AMDGPU_RAS_BLOCK__MPIO,

AMDGPU_RAS_BLOCK__LAST,

AMDGPU_RAS_BLOCK__ANY = -1

return TA_RAS_BLOCK__VCN;

case AMDGPU_RAS_BLOCK__JPEG:

return TA_RAS_BLOCK__JPEG;

default:

WARN_ONCE(1, "RAS ERROR: unexpected block id %d\n", block);

return TA_RAS_BLOCK__UMC;

size_t size, loff_t *pos)

{

struct amdgpu_ring *ring = file_inode(f)->i_private;

}

static const struct file_operations amdgpu_debugfs_mqd_fops = {

}

}

mux->s_resubmit = false;

}

#include <linux/dma-mapping.h>

#include <drm/ttm/ttm_range_manager.h>

#include "amdgpu.h"

#include "amdgpu_vm.h"

struct ttm_resource_manager *man = &mgr->manager;

int err;

ttm_resource_manager_init(man, &adev->mman.bdev,

adev->gmc.real_vram_size);

break;

case ACA_SMU_TYPE_CE:

count = ext_error_code == 6 ? count : 0ULL;

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, count);

break;

default:

break;

case AMDGPU_DPX_PARTITION_MODE:

num_xcp = 2;

break;

case AMDGPU_TPX_PARTITION_MODE:

num_xcp = 3;

static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)

{

int r, i;

for (i = 0; i < adev->gfx.num_gfx_rings; i++) {

if (r)

return r;

}

static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)

{

return 0;

}

static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)

{

gfx_v10_0_cp_compute_enable(adev, true);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

}

static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)

if (r)

return r;

if (r) {

return r;

}

return r;

}

if (r) {

return r;

}

adev->gfx.me.num_me = 1;

adev->gfx.me.num_pipe_per_me = 1;

adev->gfx.me.num_queue_per_pipe = 1;

adev->gfx.mec.num_pipe_per_mec = 4;

adev->gfx.mec.num_queue_per_pipe = 4;

break;

static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)

{

int r, i;

for (i = 0; i < adev->gfx.num_gfx_rings; i++) {

if (r)

return r;

}

static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)

{

return 0;

}

static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)

{

if (!amdgpu_async_gfx_ring)

gfx_v11_0_cp_compute_enable(adev, true);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

}

static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)

if (r)

return r;

if (r) {

return r;

}

return r;

}

if (r) {

return r;

}

r = amdgpu_mes_map_legacy_queue(adev, ring);

adev->gfx.me.num_me = 1;

adev->gfx.me.num_pipe_per_me = 1;

adev->gfx.me.num_queue_per_pipe = 1;

adev->gfx.mec.num_pipe_per_mec = 2;

adev->gfx.mec.num_queue_per_pipe = 4;

break;

static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)

{

for (i = 0; i < adev->gfx.num_gfx_rings; i++) {

if (r)

}

r = amdgpu_gfx_enable_kgq(adev, 0);

if (r)

}

static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,

static int gfx_v12_0_kiq_resume(struct amdgpu_device *adev)

{

return 0;

}

static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev)

{

if (!amdgpu_async_gfx_ring)

gfx_v12_0_cp_compute_enable(adev, true);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

}

static int gfx_v12_0_cp_resume(struct amdgpu_device *adev)

return r;

}

if (r) {

return r;

}

return r;

}

if (r) {

return r;

}

r = amdgpu_mes_map_legacy_queue(adev, ring);

static int gfx_v8_0_kiq_resume(struct amdgpu_device *adev)

{

return 0;

}

static int gfx_v8_0_kcq_resume(struct amdgpu_device *adev)

{

gfx_v8_0_cp_compute_enable(adev, true);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

gfx_v8_0_set_mec_doorbell_range(adev);

}

static int gfx_v8_0_cp_test_all_rings(struct amdgpu_device *adev)

adev->gfx.mec_fw_write_wait = false;

if ((amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 1)) &&

((adev->gfx.mec_fw_version < 0x000001a5) ||

(adev->gfx.mec_feature_version < 46) ||

(adev->gfx.pfp_fw_version < 0x000000b7) ||

static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)

{

return 0;

}

static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)

{

gfx_v9_0_cp_compute_enable(adev, true);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

}

static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)

return r;

}

if (r) {

return r;

}

spin_lock_irqsave(&kiq->ring_lock, flags);

switch (type) {

case ACA_SMU_TYPE_UE:

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type, 1ULL);

break;

case ACA_SMU_TYPE_CE:

ACA_REG__MISC0__ERRCNT(misc0));

break;

default:

static int gfx_v9_4_3_xcc_kiq_resume(struct amdgpu_device *adev, int xcc_id)

{

return 0;

}

static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id)

{

gfx_v9_4_3_xcc_cp_compute_enable(adev, true, xcc_id);

for (i = 0; i < adev->gfx.num_compute_rings; i++) {

if (r)

}

}

static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id)

return r;

}

if (r) {

return r;

}

spin_lock_irqsave(&kiq->ring_lock, flags);

1ULL);

break;

case ACA_SMU_TYPE_CE:

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

ACA_REG__MISC0__ERRCNT(misc0));

break;

{

int pipe;

/* get MES scheduler/KIQ versions */

mutex_lock(&adev->srbm_mutex);

mes_v12_0_queue_init_register(ring);

}

return 0;

}

1ULL);

break;

case ACA_SMU_TYPE_CE:

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

ACA_REG__MISC0__ERRCNT(misc0));

break;

#include "amdgpu_ucode.h"

#include "amdgpu_trace.h"

#include "amdgpu_reset.h"

#include "sdma/sdma_4_4_2_offset.h"

#include "sdma/sdma_4_4_2_sh_mask.h"

seq, 0xffffffff, 4);

}

*

*/

static void sdma_v4_4_2_ring_emit_vm_flush(struct amdgpu_ring *ring,

{

}

static void sdma_v4_4_2_ring_emit_wreg(struct amdgpu_ring *ring,

3 + /* hdp invalidate */

6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */

/* sdma_v4_4_2_ring_emit_vm_flush */

10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */

.emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */

.emit_ib = sdma_v4_4_2_ring_emit_ib,

3 + /* hdp invalidate */

6 + /* sdma_v4_4_2_ring_emit_pipeline_sync */

/* sdma_v4_4_2_ring_emit_vm_flush */

10 + 10 + 10, /* sdma_v4_4_2_ring_emit_fence x3 for user fence, vm fence */

.emit_ib_size = 7 + 6, /* sdma_v4_4_2_ring_emit_ib */

.emit_ib = sdma_v4_4_2_ring_emit_ib,

1ULL);

break;

case ACA_SMU_TYPE_CE:

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

ACA_REG__MISC0__ERRCNT(misc0));

break;

TA_RAS_BLOCK__MCA,

TA_RAS_BLOCK__VCN,

TA_RAS_BLOCK__JPEG,

TA_NUM_BLOCK_MAX

};

return (amdgpu_ras_is_poison_mode_supported(adev) &&

(REG_GET_FIELD(mc_umc_status, MCA_UMC_UMC0_MCUMC_STATUST0, Val) == 1) &&

}

bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status)

1ULL);

break;

case ACA_SMU_TYPE_CE:

ret = aca_error_cache_log_bank_error(handle, &info, bank->aca_err_type,

ACA_REG__MISC0__ERRCNT(misc0));

break;

#define HEADER_BARRIER 5

#define SDMA_OP_AQL_COPY 0

#define SDMA_OP_AQL_BARRIER_OR 0

/*define for op field*/

#define SDMA_PKT_HEADER_op_offset 0

#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift 0

#define SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_COMPLETION_SIGNAL_63_32(x) (((x) & SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_mask) << SDMA_AQL_PKT_BARRIER_OR_COMPLETION_SIGNAL_HI_completion_signal_63_32_shift)

#endif /* __SDMA_PKT_OPEN_H_ */

if (kfd_dbg_has_ttmps_always_setup(dev->gpu))

dev->node_props.debug_prop |= HSA_DBG_DISPATCH_INFO_ALWAYS_VALID;

if (KFD_GC_VERSION(dev->gpu) < IP_VERSION(10, 0, 0)) {

if (KFD_GC_VERSION(dev->gpu) == IP_VERSION(9, 4, 3) ||

KFD_GC_VERSION(dev->gpu) == IP_VERSION(9, 4, 4))

dev->node_props.capability |=

HSA_CAP_TRAP_DEBUG_PRECISE_MEMORY_OPERATIONS_SUPPORTED;

} else {

dev->node_props.debug_prop |= HSA_DBG_WATCH_ADDR_MASK_LO_BIT_GFX10 |

HSA_DBG_WATCH_ADDR_MASK_HI_BIT;

.callback = edp0_on_dp1_callback,

.matches = {

DMI_MATCH(DMI_SYS_VENDOR, "HP"),

DMI_MATCH(DMI_PRODUCT_NAME, "HP EliteBook 665 16 inch G11 Notebook PC"),

},

},

{}

/* TODO: refactor this from a fixed table to a dynamic option */

};

int offdelay;

if (acrtc_state) {

offdelay = DIV64_U64_ROUND_UP((u64)20 *

timing->v_total *

timing->h_total,

config.offdelay_ms = offdelay ?: 30;

} else {

config.disable_immediate = true;

}

*

* Panel Replay and PSR SU

* - Enable when:

* - vblank counter is disabled

* - entry is allowed: usermode demonstrates an adequate number of fast

* commits)

bool is_sr_active = (link->replay_settings.replay_allow_active ||

link->psr_settings.psr_allow_active);

bool is_crc_window_active = false;

#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY

is_crc_window_active =

amdgpu_dm_crc_window_is_activated(&vblank_work->acrtc->base);

#endif

allow_sr_entry && !is_sr_active && !is_crc_window_active) {

amdgpu_dm_replay_enable(vblank_work->stream, true);

} else if (vblank_enabled) {

if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)

amdgpu_dm_psr_disable(vblank_work->stream, false);

allow_sr_entry && !is_sr_active && !is_crc_window_active) {

struct amdgpu_dm_connector *aconn =

struct vblank_control_work *vblank_work =

container_of(work, struct vblank_control_work, work);

struct amdgpu_display_manager *dm = vblank_work->dm;

mutex_lock(&dm->dc_lock);

vblank_work->acrtc->dm_irq_params.allow_sr_entry);

}

dc_allow_idle_optimizations(dm->dc, true);

mutex_unlock(&dm->dc_lock);

/* Store configuration options */

(*dml_ctx)->config = *config;

/*Initialize SOCBB and DCNIP params */

dml21_initialize_soc_bb_params(&(*dml_ctx)->v21.dml_init, config, in_dc);

dml21_initialize_ip_params(&(*dml_ctx)->v21.dml_init, config, in_dc);

/*Initialize DML21 instance */

dml2_initialize_instance(&(*dml_ctx)->v21.dml_init);

}

bool dml21_create(const struct dc *in_dc, struct dml2_context **dml_ctx, const struct dml2_configuration_options *config)

{

bool out = false;

/* Use dml_validate_only for fast_validate path */

out = dml21_check_mode_support(in_dc, context, dml_ctx);

out = dml21_mode_check_and_programming(in_dc, context, dml_ctx);

return out;

}

dst_dml_ctx->v21.mode_programming.programming = dst_dml2_programming;

/* need to initialize copied instance for internal references to be correct */

dml2_initialize_instance(&dst_dml_ctx->v21.dml_init);

}

bool dml21_create_copy(struct dml2_context **dst_dml_ctx,

p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;

p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;

p->out_states->state_array[i].phyclk_mhz = max_phyclk_mhz;

p->out_states->state_array[i].dtbclk_mhz = max_dtbclk_mhz;

/* Dependent states. */

p->out_states->state_array[i].dram_speed_mts = p->in_states->state_array[i].dram_speed_mts;

p->out_states->state_array[i].fabricclk_mhz = p->in_states->state_array[i].fabricclk_mhz;

p->out_states->state_array[i].socclk_mhz = p->in_states->state_array[i].socclk_mhz;

return out;

}

/* Use dml_validate_only for fast_validate path */

if (fast_validate)

out = dml2_validate_only(context);

else

out = dml2_validate_and_build_resource(in_dc, context);

return out;

}

break;

}

initialize_dml2_ip_params(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.ip);

initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc);

initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states);

}

bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)

dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);

phyd32clk = get_phyd32clk_src(link);

} else {

if (dccg->funcs->enable_symclk_se)

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {

if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst);

} else {

dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

link_enc->transmitter - TRANSMITTER_UNIPHY_A);

#define MAX_CLKS 4

#define NUM_VCN 4

#define NUM_JPEG_ENG 32

#define MAX_XCC 8

#define NUM_XCP 8

struct seq_file;

uint64_t gfx_below_host_limit_acc[MAX_XCC];

};

struct amd_pm_funcs {

/* export for dpm on ci and si */

int (*pre_set_power_state)(void *handle);

int (*set_pp_table)(void *handle, const char *buf, size_t size);

void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);

int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);

/* export to amdgpu */

struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);

int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,

uint32_t pcie_lc_perf_other_end_recovery;

};

/*

* gpu_metrics_v2_0 is not recommended as it's not naturally aligned.

* Use gpu_metrics_v2_1 or later instead.

return ret;

}

int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,

uint32_t pstate)

{

int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,

enum PP_SMC_POWER_PROFILE type,

bool en);

int amdgpu_dpm_baco_reset(struct amdgpu_device *adev);

if (hwmgr->thermal_controller.fanInfo.bNoFan ||

(hwmgr->thermal_controller.fanInfo.

ucTachometerPulsesPerRevolution == 0) ||

(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||

(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))

if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))

smu7_fan_ctrl_stop_smc_fan_control(hwmgr);

int result = 0;

if (hwmgr->thermal_controller.fanInfo.bNoFan ||

(speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||

(speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))

if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))

result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);

uint32_t tach_period, crystal_clock_freq;

int result = 0;

return -EINVAL;

if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {

smu_power_profile_mode_get(smu, type);

else

smu_power_profile_mode_put(smu, type);

if (ret) {

if (enable)

smu_power_profile_mode_put(smu, type);

return 0;

}

static enum amd_dpm_forced_level smu_get_performance_level(void *handle)

{

struct smu_context *smu = handle;

.get_pp_table = smu_sys_get_pp_table,

.set_pp_table = smu_sys_set_pp_table,

.switch_power_profile = smu_switch_power_profile,

/* export to amdgpu */

.dispatch_tasks = smu_handle_dpm_task,

.load_firmware = smu_load_microcode,

/* asic agnostic workload mask */

uint32_t workload_mask;

/* default/user workload preference */

uint32_t power_profile_mode;

uint32_t workload_refcount[PP_SMC_POWER_PROFILE_COUNT];

VOLTAGE_GUARDBAND_COUNT

} GFX_GUARDBAND_e;

// Unified metrics table for smu_v13_0_6

typedef struct __attribute__((packed, aligned(4))) {

uint32_t PCIeOtherEndRecoveryAcc; // The Pcie counter itself is accumulated

//Total App Clock Counter

} MetricsTableV0_t;

// Metrics table for smu_v13_0_6 APUS

uint32_t crystal_clock_freq = 2500;

uint32_t tach_period;

tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);

WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,

REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),

uint32_t crystal_clock_freq = 2500;

uint32_t tach_period;

return -EINVAL;

/*

* To prevent from possible overheat, some ASICs may have requirement

uint32_t tach_period;

int ret;

return -EINVAL;

ret = smu_v13_0_auto_fan_control(smu, 0);

SMU_CAP(OTHER_END_METRICS),

SMU_CAP(SET_UCLK_MAX),

SMU_CAP(PCIE_METRICS),

SMU_CAP(MCA_DEBUG_MODE),

SMU_CAP(PER_INST_METRICS),

SMU_CAP(CTF_LIMIT),

if (fw_ver >= 0x05550E00)

smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));

if (fw_ver >= 0x05550B00)

smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));

if (fw_ver >= 0x5551200)

SMU_CAP(RMA_MSG),

SMU_CAP(ACA_SYND),

SMU_CAP(OTHER_END_METRICS),

SMU_CAP(PER_INST_METRICS) };

uint32_t fw_ver = smu->smc_fw_version;

smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));

smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));

if (fw_ver >= 0x04556A00)

smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));

} else {

smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));

if (fw_ver < 0x00555600)

smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));

}

if (((pgm == 7) && (fw_ver >= 0x7550700)) ||

((pgm == 0) && (fw_ver >= 0x00557900)) ||

gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] =

SMUQ10_ROUND(GET_GPU_METRIC_FIELD(GfxBusyAcc,

version)[inst]);

idx++;

}

}

#define PP_OD_FEATURE_FAN_ACOUSTIC_TARGET 8

#define PP_OD_FEATURE_FAN_TARGET_TEMPERATURE 9

#define PP_OD_FEATURE_FAN_MINIMUM_PWM 10

static struct cmn2asic_msg_mapping smu_v14_0_2_message_map[SMU_MSG_MAX_COUNT] = {

MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),

od_min_setting = overdrive_lowerlimits->FanMinimumPwm;

od_max_setting = overdrive_upperlimits->FanMinimumPwm;

break;

default:

od_min_setting = od_max_setting = INT_MAX;

break;

min_value, max_value);

break;

case SMU_OD_RANGE:

if (!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_GFXCLK_BIT) &&

!smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_UCLK_BIT) &&

OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_RETRIEVE |

OD_OPS_SUPPORT_FAN_TARGET_TEMPERATURE_SET |

OD_OPS_SUPPORT_FAN_MINIMUM_PWM_RETRIEVE |

}

static int smu_v14_0_2_get_overdrive_table(struct smu_context *smu,

user_od_table_bak.OverDriveTable.FanTargetTemperature;

user_od_table->OverDriveTable.FanMinimumPwm =

user_od_table_bak.OverDriveTable.FanMinimumPwm;

}

smu_v14_0_2_set_supported_od_feature_mask(smu);

od_table->OverDriveTable.FanMode = FAN_MODE_AUTO;

od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);

break;

case PP_OD_EDIT_ACOUSTIC_LIMIT:

od_table->OverDriveTable.AcousticLimitRpmThreshold =

boot_overdrive_table->OverDriveTable.AcousticLimitRpmThreshold;

od_table->OverDriveTable.FeatureCtrlMask |= BIT(PP_OD_FEATURE_FAN_CURVE_BIT);

break;

case PP_OD_RESTORE_DEFAULT_TABLE:

if (size == 1) {

ret = smu_v14_0_2_od_restore_table_single(smu, input[0]);

case METRICS_VERSION(1, 7):

structure_size = sizeof(struct gpu_metrics_v1_7);

break;

case METRICS_VERSION(2, 0):

structure_size = sizeof(struct gpu_metrics_v2_0);

break;

Support for i.MX8MP DPI-to-LVDS on-SoC encoder.

config DRM_I2C_NXP_TDA998X

config DRM_ITE_IT6263

tristate "ITE IT6263 LVDS/HDMI bridge"

if (priv->hdmi->irq)

free_irq(priv->hdmi->irq, priv);

cancel_work_sync(&priv->detect_work);

i2c_unregister_device(priv->cec);

drm_core_check_feature(dev, DRIVER_MODESET));

drm_vblank_destroy_worker(vblank);

}

/**

{

struct vidi_context *ctx = dev_get_drvdata(dev);

}

static const struct component_ops vidi_component_ops = {

usb_sg_wait(&ctx.sgr);

ret = -ETIMEDOUT;

else if (ctx.sgr.status < 0)

ret = ctx.sgr.status;

qi->deinterleave = 4;

break;

case INTEL_DRAM_GDDR:

qi->channel_width = 32;

break;

default:

/* Other values not used by simplified algorithm */

};

static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)

{

struct intel_qgv_info qi = {};

void intel_bw_init_hw(struct drm_i915_private *dev_priv)

{

if (!HAS_DISPLAY(dev_priv))

return;

xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info);

else if (DISPLAY_VER(dev_priv) >= 14)

tgl_get_bw_info(dev_priv, &mtl_sa_info);

old_crtc_state->vrr.vmin != new_crtc_state->vrr.vmin ||

old_crtc_state->vrr.vmax != new_crtc_state->vrr.vmax ||

old_crtc_state->vrr.guardband != new_crtc_state->vrr.guardband ||

}

static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,

static int max_dprx_rate(struct intel_dp *intel_dp)

{

if (intel_dp_tunnel_bw_alloc_is_enabled(intel_dp))

}

static int max_dprx_lane_count(struct intel_dp *intel_dp)

static void

intel_edp_set_sink_rates(struct intel_dp *intel_dp)

{

intel_dp->num_sink_rates = 0;

if (intel_dp->edp_dpcd[0] >= DP_EDP_14) {

sink_rates, sizeof(sink_rates));

for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {

/* Value read multiplied by 200kHz gives the per-lane

* link rate in kHz. The source rates are, however,

* back to symbols is

* (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)

*/

}

intel_dp->num_sink_rates = i;

}

#ifndef __INTEL_FBDEV_H__

#define __INTEL_FBDEV_H__

struct drm_fb_helper;

struct drm_fb_helper_surface_size;

struct drm_i915_private;

* However if queried just before the start of vblank we'll get an

* answer that's slightly in the future.

*/

return -1;

else if (HAS_DDI(display) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))

return 2;

static int

dsc_prefill_latency(const struct intel_crtc_state *crtc_state)

{

const struct intel_crtc_scaler_state *scaler_state =

&crtc_state->scaler_state;

int linetime = DIV_ROUND_UP(1000 * crtc_state->hw.adjusted_mode.htotal,

crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ? 2 : 1;

u32 dsc_prefill_latency = 0;

return dsc_prefill_latency;

dsc_prefill_latency = DIV_ROUND_UP(15 * linetime * chroma_downscaling_factor, 10);

ENGINE_READ_FW(engine, RING_EXECLIST_STATUS_HI));

ENGINE_TRACE(engine, "semaphore yield: %08x\n",

engine->execlists.yield);

tasklet = true;

}

static void execlists_shutdown(struct intel_engine_cs *engine)

{

/* Synchronise with residual timers and any softirq they raise */

tasklet_kill(&engine->sched_engine->tasklet);

}

GEN6_RC_CTL_RC6_ENABLE |

GEN6_RC_CTL_EI_MODE(1);

if (GRAPHICS_VER(gt->i915) >= 12 && !IS_DG1(gt->i915)) {

for (i = 0; i < I915_MAX_VCS; i++)

static void rps_stop_timer(struct intel_rps *rps)

{

rps->pm_timestamp = ktime_sub(ktime_get(), rps->pm_timestamp);

cancel_work_sync(&rps->work);

}

struct i915_request *rq;

unsigned long flags;

spin_lock_irqsave(&engine->sched_engine->lock, flags);

container_of(engine, typeof(*mock), base);

struct i915_request *request, *rn;

spin_lock_irq(&mock->hw_lock);

list_for_each_entry_safe(request, rn, &mock->hw_queue, mock.link)

ENGINE_TRACE(engine, "forcing tasklet for rewind\n");

while (i915_request_is_active(rq[A2])) { /* semaphore yield! */

/* Wait for the timeslice to kick in */

tasklet_hi_schedule(&engine->sched_engine->tasklet);

intel_engine_flush_submission(engine);

}

/* force preempt reset [failure] */

while (!engine->execlists.pending[0])

intel_engine_flush_submission(engine);

intel_engine_flush_submission(engine);

cancel_reset_timeout(engine);

out_rq:

i915_request_add(rq); /* GEM_BUG_ON(rq->reserved_space > ring->space)? */

destroy_timer_on_stack(&st.timer);

out_unpin:

intel_context_unpin(ce);

}

}

#define HUC_LOAD_MODE_STRING(x) (x ? "GSC" : "legacy")

static int check_huc_loading_mode(struct intel_huc *huc)

{

void intel_huc_fini(struct intel_huc *huc)

{

if (huc->heci_pkt)

i915_vma_unpin_and_release(&huc->heci_pkt, 0);

int intel_huc_sanitize(struct intel_huc *huc);

void intel_huc_init_early(struct intel_huc *huc);

int intel_huc_init(struct intel_huc *huc);

void intel_huc_fini(struct intel_huc *huc);

int intel_huc_auth(struct intel_huc *huc, enum intel_huc_authentication_type type);

void intel_uc_driver_late_release(struct intel_uc *uc)

{

}

/**

u8 *buf;

struct opregion_header *header;

struct vbt v;

gvt_dbg_core("init vgpu%d opregion\n", vgpu->id);

vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_KERNEL |

/* emulated opregion with VBT mailbox only */

buf = (u8 *)vgpu_opregion(vgpu)->va;

header = (struct opregion_header *)buf;

header->size = 0x8;

header->opregion_ver = 0x02000000;

header->mboxes = MBOX_VBT;

INTEL_DRAM_DDR5,

INTEL_DRAM_LPDDR5,

INTEL_DRAM_GDDR,

} type;

u8 num_qgv_points;

u8 num_psf_gv_points;

if (!timer_active(t))

return;

WRITE_ONCE(t->expires, 0);

}

unsigned long flags;

if (!timeout) {

wakeref_auto_timeout(&wf->timer);

return;

}

#include <linux/random.h>

#include "gt/intel_gt_pm.h"

#include "gt/uc/intel_gsc_fw.h"

#include "i915_driver.h"

int i915_live_selftests(struct pci_dev *pdev)

{

struct drm_i915_private *i915 = pdev_to_i915(pdev);

int err;

if (!i915_selftest.live)

return 0;

__wait_gsc_proxy_completed(i915);

__wait_gsc_huc_load_completed(i915);

void timed_fence_fini(struct timed_fence *tf)

{

i915_sw_fence_commit(&tf->fence);

destroy_timer_on_stack(&tf->timer);

drm_WARN_ON(&i915->drm, !IS_DGFX(i915));

dram_info->type = INTEL_DRAM_GDDR;

break;

default:

MISSING_CASE(val);

return -EINVAL;

fw_mem->core_data, fw_mem->core_code_alloc_size);

if (err)

memcpy(fw_code_ptr, fw_mem->code, fw_mem->code_alloc_size);

memcpy(fw_data_ptr, fw_mem->data, fw_mem->data_alloc_size);

memcpy(fw_core_data_ptr, fw_mem->core_data, fw_mem->core_data_alloc_size);

/* We're finished with the firmware section memory on the CPU, unmap. */

pvr_fw_object_vunmap(fw_mem->core_data_obj);

pvr_fw_object_vunmap(fw_mem->core_code_obj);

pvr_fw_object_vunmap(fw_mem->data_obj);

fw_data_ptr = NULL;

pvr_fw_object_vunmap(fw_mem->code_obj);

err = pvr_fw_create_fwif_connection_ctl(pvr_dev);

if (err)

return 0;

kfree(fw_mem->data);

kfree(fw_mem->code);

if (fw_core_data_ptr)

err_free_fw_core_code_obj:

if (fw_core_code_ptr)

err_free_fw_data_obj:

if (fw_data_ptr)

struct pvr_fw_mem *fw_mem = &pvr_dev->fw_dev.mem;

pvr_fw_fini_fwif_connection_ctl(pvr_dev);

if (fw_mem->core_code_obj)

pvr_fw_object_destroy(fw_mem->core_code_obj);

if (fw_mem->core_data_obj)

geom_job->paired_job = frag_job;

frag_job->paired_job = geom_job;

/* Skip the fragment job we just paired to the geometry job. */

i++;

}

struct pvr_job *job = container_of(sched_job, struct pvr_job, base);

drm_sched_job_cleanup(sched_job);

job->paired_job = NULL;

pvr_job_put(job);

}

pm_runtime_put(&pdev->dev);

pm_runtime_disable(&pdev->dev);

if (mtk_dp->data->bridge_type != DRM_MODE_CONNECTOR_eDP)

platform_device_unregister(mtk_dp->phy_dev);

if (mtk_dp->audio_pdev)

platform_device_unregister(mtk_dp->audio_pdev);

gpu_read(gpu, REG_A5XX_CP_IB2_BUFSZ));

/* Turn off the hangcheck timer to keep it from bothering us */

kthread_queue_work(gpu->worker, &gpu->recover_work);

}

return;

/* Delete the preemption watchdog timer */

/*

* The hardware should be setting CP_CONTEXT_SWITCH_CNTL to zero before

gmu->hung = true;

/* Turn off the hangcheck timer while we are resetting */

/* Queue the GPU handler because we need to treat this as a recovery */

kthread_queue_work(gpu->worker, &gpu->recover_work);

gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));

/* Turn off the hangcheck timer to keep it from bothering us */

kthread_queue_work(gpu->worker, &gpu->recover_work);

}

*/

if (status & (A7XX_CX_MISC_SW_FUSE_VALUE_RAYTRACING |

A7XX_CX_MISC_SW_FUSE_VALUE_LPAC)) {

kthread_queue_work(gpu->worker, &gpu->recover_work);

}

return;

/* Delete the preemption watchdog timer */

/*

* The hardware should be setting the stop bit of CP_CONTEXT_SWITCH_CNTL

if (do_devcoredump) {

/* Turn off the hangcheck timer to keep it from bothering us */

gpu->fault_info.ttbr0 = info->ttbr0;

gpu->fault_info.iova = iova;

/* after phys waits for frame-done, should be no more frames pending */

if (atomic_xchg(&dpu_enc->frame_done_timeout_ms, 0)) {

DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);

}

dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_STOP);

if (!dpu_enc->frame_busy_mask[0]) {

atomic_set(&dpu_enc->frame_done_timeout_ms, 0);

dpu_encoder_resource_control(drm_enc,

DPU_ENC_RC_EVENT_FRAME_DONE);

nouveau_bo_del_io_reserve_lru(bo);

nv10_bo_put_tile_region(dev, nvbo->tile, NULL);

/*

* If nouveau_bo_new() allocated this buffer, the GEM object was never

* initialized, so don't attempt to release it.

return;

}

ttm_bo_put(&nvbo->bo);

pm_runtime_mark_last_busy(dev);

#ifdef DSI_CATCH_MISSING_TE

if (irqstatus & DSI_IRQ_TE_TRIGGER)

#endif

/* make a copy and unlock, so that isrs can unregister

struct gpio_desc *enable_gpio;

struct delayed_work hpd_work;

int port_id;

};

struct rockchip_hdmi_qp_ctrl_ops {

return -ENODEV;

}

hdmi->dev = &pdev->dev;

hdmi->port_id = -ENODEV;

static int __maybe_unused dw_hdmi_qp_rockchip_resume(struct device *dev)

{

struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev);

dw_hdmi_qp_resume(dev, hdmi->hdmi);

dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP0_PIN_POL, polflags);

break;

case ROCKCHIP_VOP2_EP_DP1:

dip &= ~RK3588_DSP_IF_POL__DP1_PIN_POL;

dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP1_PIN_POL, polflags);

break;

sti_compositor.o \

sti_crtc.o \

sti_plane.o \

sti_hdmi.o \

sti_hdmi_tx3g4c28phy.o \

sti_dvo.o \

expected_mode = drm_mode_find_dmt(priv->drm, 1920, 1080, 60, false);

KUNIT_ASSERT_NOT_NULL(test, expected_mode);

KUNIT_ASSERT_TRUE(test,

drm_mode_parse_command_line_for_connector(cmdline,

connector,

struct drm_device *drm = priv->drm;

struct drm_connector *connector = &priv->connector;

struct drm_cmdline_mode *cmdline_mode = &connector->cmdline_mode;

const char *cmdline = params->cmdline;

int ret;

expected_mode = params->func(drm);

KUNIT_ASSERT_NOT_NULL(test, expected_mode);

KUNIT_EXPECT_TRUE(test, drm_mode_equal(expected_mode, mode));

}

#include <kunit/test.h>

#include <drm/drm_connector.h>

#include <drm/drm_modes.h>

static const struct drm_connector no_connector = {};

static void drm_test_cmdline_tv_options(struct kunit *test)

{

const struct drm_cmdline_tv_option_test *params = test->param_value;

struct drm_cmdline_mode mode = { };

KUNIT_EXPECT_TRUE(test, drm_mode_parse_command_line_for_connector(params->cmdline,

&no_connector, &mode));

}

/**

* drm_kunit_display_mode_from_cea_vic() - return a mode for CEA VIC for a KUnit test

* @test: The test context object

* @dev: DRM device

{

struct drm_test_modes_priv *priv = test->priv;

struct drm_display_mode *mode;

mode = drm_analog_tv_mode(priv->drm,

DRM_MODE_TV_MODE_NTSC,

true);

KUNIT_ASSERT_NOT_NULL(test, mode);

KUNIT_EXPECT_EQ(test, drm_mode_vrefresh(mode), 60);

KUNIT_EXPECT_EQ(test, mode->hdisplay, 720);

{

struct drm_test_modes_priv *priv = test->priv;

struct drm_display_mode *expected, *mode;

expected = drm_analog_tv_mode(priv->drm,

DRM_MODE_TV_MODE_NTSC,

true);

KUNIT_ASSERT_NOT_NULL(test, expected);

mode = drm_mode_analog_ntsc_480i(priv->drm);

KUNIT_ASSERT_NOT_NULL(test, mode);

KUNIT_EXPECT_TRUE(test, drm_mode_equal(expected, mode));

}

{

struct drm_test_modes_priv *priv = test->priv;

struct drm_display_mode *mode;

mode = drm_analog_tv_mode(priv->drm,

DRM_MODE_TV_MODE_PAL,

true);

KUNIT_ASSERT_NOT_NULL(test, mode);

KUNIT_EXPECT_EQ(test, drm_mode_vrefresh(mode), 50);

KUNIT_EXPECT_EQ(test, mode->hdisplay, 720);

{

struct drm_test_modes_priv *priv = test->priv;

struct drm_display_mode *expected, *mode;

expected = drm_analog_tv_mode(priv->drm,

DRM_MODE_TV_MODE_PAL,

true);

KUNIT_ASSERT_NOT_NULL(test, expected);

mode = drm_mode_analog_pal_576i(priv->drm);

KUNIT_ASSERT_NOT_NULL(test, mode);

KUNIT_EXPECT_TRUE(test, drm_mode_equal(expected, mode));

}

{

struct drm_test_modes_priv *priv = test->priv;

struct drm_display_mode *mode;

mode = drm_analog_tv_mode(priv->drm,

DRM_MODE_TV_MODE_MONOCHROME,

true);

KUNIT_ASSERT_NOT_NULL(test, mode);

KUNIT_EXPECT_EQ(test, drm_mode_vrefresh(mode), 50);

KUNIT_EXPECT_EQ(test, mode->hdisplay, 720);

struct drm_connector *connector = &priv->connector;

struct drm_cmdline_mode *cmdline = &connector->cmdline_mode;

struct drm_display_mode *mode;

size_t len;

int ret;

KUNIT_EXPECT_TRUE(test, drm_mode_equal(mode, expected));

KUNIT_EXPECT_TRUE(test, mode->type & DRM_MODE_TYPE_PREFERRED);

}

if (params->num_expected_modes >= 2) {

KUNIT_EXPECT_TRUE(test, drm_mode_equal(mode, expected));

KUNIT_EXPECT_FALSE(test, mode->type & DRM_MODE_TYPE_PREFERRED);

}

mutex_unlock(&priv->drm->mode_config.mutex);

struct vc4_dev *vc4 = to_vc4_dev(dev);

int i;

cancel_work_sync(&vc4->bo_cache.time_work);

vc4_bo_cache_purge(dev);

{

struct vgem_fence *fence = container_of(base, typeof(*fence), base);

dma_fence_free(&fence->base);

}

if (!vgdev->has_context_init)

virtio_gpu_create_context(obj->dev, file);

virtio_gpu_cmd_context_attach_resource(vgdev, vfpriv->ctx_id, objs);

out_notify:

virtio_gpu_notify(vgdev);

return 0;

obj = new_state->fb->obj[0];

if (bo->dumb || obj->import_attach) {

vgplane_st->fence = virtio_gpu_fence_alloc(vgdev,

vgdev->fence_drv.context,

return -ENOMEM;

}

return 0;

}

static void virtio_gpu_cleanup_imported_obj(struct drm_gem_object *obj)

return ERR_PTR(-ENOMEM);

obj = &bo->base.base;

obj->funcs = &virtgpu_gem_dma_buf_funcs;

drm_gem_private_object_init(dev, obj, buf->size);

config DRM_XE_DISPLAY

bool "Enable display support"

depends on DRM_XE && DRM_XE=m && HAS_IOPORT

select I2C

select I2C_ALGOBIT

default y

#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2))

#define PIPE_CONTROL0_HDC_PIPELINE_FLUSH BIT(9) /* gen12 */

#define PIPE_CONTROL_COMMAND_CACHE_INVALIDATE (1<<29)

#define RING_EXECLIST_STATUS_LO(base) XE_REG((base) + 0x234)

#define RING_EXECLIST_STATUS_HI(base) XE_REG((base) + 0x234 + 4)

#define RING_CONTEXT_CONTROL(base) XE_REG((base) + 0x244, XE_REG_OPTION_MASKED)

#define CTX_CTRL_PXP_ENABLE REG_BIT(10)

#define CTX_CTRL_OAC_CONTEXT_ENABLE REG_BIT(8)

#include "xe_pxp.h"

#include "xe_query.h"

#include "xe_shrinker.h"

#include "xe_sriov.h"

#include "xe_tile.h"

#include "xe_ttm_stolen_mgr.h"

sriov_update_device_info(xe);

err = xe_pcode_probe_early(xe);

err = wait_for_lmem_ready(xe);

if (err)

INTEL_DRAM_DDR5,

INTEL_DRAM_LPDDR5,

INTEL_DRAM_GDDR,

} type;

u8 num_qgv_points;

u8 num_psf_gv_points;

goto exit_free;

}

exit_free:

mutex_destroy(&gt->eu_stall->stream_lock);

kfree(gt->eu_stall);

void xe_execlist_port_destroy(struct xe_execlist_port *port)

{

/* Prevent an interrupt while we're destroying */

spin_lock_irq(&gt_to_xe(port->hwe->gt)->irq.lock);

#include "xe_macros.h"

#include "xe_mmio.h"

{

u32 crystal_clock = REG_FIELD_GET(RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK,

rpm_config_reg);

switch (crystal_clock) {

case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:

case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:

case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:

case RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:

default:

}

}

{

/*

* CTC_MODE[0] = 1 is definitely not supported for Xe2 and later

* platforms. In theory it could be a valid setting for pre-Xe2

*/

if (xe_mmio_read32(&gt->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC)

xe_gt_warn(gt, "CTC_MODE[0] is set; this is unexpected and undocumented\n");

/*

* Now figure out how the command stream's timestamp

return 0;

}

/**

* xe_gt_tlb_invalidation_range - Issue a TLB invalidation on this GT for an

* address range

struct xe_device *xe = gt_to_xe(gt);

#define MAX_TLB_INVALIDATION_LEN 7

u32 action[MAX_TLB_INVALIDATION_LEN];

int len = 0;

xe_gt_assert(gt, fence);

action[len++] = XE_GUC_ACTION_TLB_INVALIDATION;

action[len++] = 0; /* seqno, replaced in send_tlb_invalidation */

action[len++] = MAKE_INVAL_OP(XE_GUC_TLB_INVAL_FULL);

} else {

u64 orig_start = start;

u64 align;

if (length < SZ_4K)

enum xe_gt_type type;

/** @info.reference_clock: clock frequency */

u32 reference_clock;

/**

* @info.engine_mask: mask of engines present on GT. Some of

* them may be reserved in runtime and not available for user.

if (wait_for_pc_state(pc, SLPC_GLOBAL_STATE_RUNNING,

SLPC_RESET_EXTENDED_TIMEOUT_MS)) {

xe_gt_err(gt, "GuC PC Start failed: Dynamic GT frequency control and GT sleep states are now disabled.\n");

goto out;

}

#include <linux/nospec.h>

#include <drm/drm_managed.h>

#include <uapi/drm/xe_drm.h>

#include "regs/xe_engine_regs.h"

#include "regs/xe_gt_regs.h"

#include "xe_gsc.h"

#include "xe_gt.h"

#include "xe_gt_ccs_mode.h"

#include "xe_gt_printk.h"

#include "xe_gt_mcr.h"

#include "xe_gt_topology.h"

blit_cctl_val,

XE_RTP_ACTION_FLAG(ENGINE_BASE)))

},

/* Disable WMTP if HW doesn't support it */

{ XE_RTP_NAME("DISABLE_WMTP_ON_UNSUPPORTED_HW"),

XE_RTP_RULES(FUNC(xe_rtp_cfeg_wmtp_disabled)),

XE_RTP_ACTIONS(SET(CSFE_CHICKEN1(0), CS_PRIORITY_MEM_READ,

XE_RTP_ACTION_FLAG(ENGINE_BASE)))

},

};

xe_rtp_process_to_sr(&ctx, engine_entries, ARRAY_SIZE(engine_entries), &hwe->reg_sr);

xe_reg_whitelist_process_engine(hwe);

}

static int hw_engine_init(struct xe_gt *gt, struct xe_hw_engine *hwe,

enum xe_hw_engine_id id)

{

if (xe->info.has_usm && hwe->class == XE_ENGINE_CLASS_COPY)

gt->usm.reserved_bcs_instance = hwe->instance;

return devm_add_action_or_reset(xe->drm.dev, hw_engine_fini, hwe);

err_hwsp:

return timeout >= min && timeout <= max;

}

{

kfree(kobj);

}

static const struct kobj_type kobj_xe_hw_engine_type = {

};

static ssize_t job_timeout_max_store(struct kobject *kobj,

if (!kobj)

return -ENOMEM;

err = kobject_add(kobj, parent, "%s", ".defaults");

if (err)

goto err_object;

return err;

}

static void hw_engine_class_sysfs_fini(void *arg)

{

if (!kobj)

return -ENOMEM;

err = kobject_add(kobj, gt->sysfs, "engines");

if (err)

err_sync:

/* Sync partial copies if any. FIXME: job_mutex? */

if (fence) {

dma_fence_put(fence);

}

static u32 pte_update_cmd_size(u64 size)

{

u32 num_dword;

XE_WARN_ON(size > MAX_PREEMPTDISABLE_TRANSFER);

/*

* 2 dword for the page table's physical location

* 2*n dword for value of pte to fill (each pte entry is 2 dwords)

*/

num_dword += entries * 2;

return num_dword;

return err;

err = xe_device_probe_early(xe);

if (err) {

return 0;

return err;

static int emit_pipe_invalidate(u32 mask_flags, bool invalidate_tlb, u32 *dw,

int i)

{

PIPE_CONTROL_COMMAND_CACHE_INVALIDATE |

PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |

PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |

PIPE_CONTROL_STORE_DATA_INDEX;

if (invalidate_tlb)

}

static int emit_store_imm_ppgtt_posted(u64 addr, u64 value,

if (ret)

return ret;

ret = xe_heci_gsc_init(xe);

return ret;

xe_vsec_init(xe);

dev_err(dev, "In Survivability Mode\n");

return 0;

return xe->survivability.mode;

}

*

*

*/

{

struct xe_survivability *survivability = &xe->survivability;

struct xe_mmio *mmio = xe_root_tile_mmio(xe);

*

* Initialize survivability information and enable survivability mode

*

*/

int xe_survivability_mode_enable(struct xe_device *xe)

{

struct xe_survivability_info *info;

struct pci_dev *pdev = to_pci_dev(xe->drm.dev);

survivability->size = MAX_SCRATCH_MMIO;

info = devm_kcalloc(xe->drm.dev, survivability->size, sizeof(*info),

int xe_survivability_mode_enable(struct xe_device *xe);

bool xe_survivability_mode_is_enabled(struct xe_device *xe);

#endif /* _XE_SURVIVABILITY_MODE_H_ */

list_for_each_entry(block, blocks, link)

block->private = vr;

err = drm_gpusvm_migrate_to_devmem(&vm->svm.gpusvm, &range->base,

&bo->devmem_allocation, ctx);

if (err)

unlock:

mmap_read_unlock(mm);

FUNC(xe_rtp_match_first_render_or_compute)),

XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN, RES_CHK_SPR_DIS))

},

};

static const struct xe_rtp_entry_sr lrc_was[] = {

GRAPHICS_VERSION(3001)

14022293748 GRAPHICS_VERSION(2001)

GRAPHICS_VERSION(2004)

22019794406 GRAPHICS_VERSION(2001)

GRAPHICS_VERSION(2004)

22019338487 MEDIA_VERSION(2000)

GRAPHICS_VERSION(2001)

MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_not_sriov_vf)

GRAPHICS_VERSION_RANGE(1270, 1274)

1508761755 GRAPHICS_VERSION(1255)

GRAPHICS_VERSION(1260), GRAPHICS_STEP(A0, B0)