diff options
Diffstat (limited to 'drivers/gpu/drm/nouveau/nvkm/engine/device/base.c')
| -rw-r--r-- | drivers/gpu/drm/nouveau/nvkm/engine/device/base.c | 134 |
1 files changed, 67 insertions, 67 deletions
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c index fa4a1f00499c..ea3e8902f458 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c @@ -86,7 +86,7 @@ nv4_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv04_fifo_new, // .gr = nv04_gr_new, @@ -106,7 +106,7 @@ nv5_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv04_fifo_new, // .gr = nv04_gr_new, @@ -127,7 +127,7 @@ nv10_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .gr = nv10_gr_new, }; @@ -146,7 +146,7 @@ nv11_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv10_fifo_new, // .gr = nv10_gr_new, @@ -167,7 +167,7 @@ nv15_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv10_fifo_new, // .gr = nv10_gr_new, @@ -188,7 +188,7 @@ nv17_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv10_gr_new, @@ -209,7 +209,7 @@ nv18_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv10_gr_new, @@ -230,7 +230,7 @@ nv1a_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv10_fifo_new, // .gr = nv10_gr_new, @@ -251,7 +251,7 @@ nv1f_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv10_gr_new, @@ -272,7 +272,7 @@ nv20_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv20_gr_new, @@ -293,7 +293,7 @@ nv25_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv25_gr_new, @@ -314,7 +314,7 @@ nv28_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv25_gr_new, @@ -335,7 +335,7 @@ nv2a_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv2a_gr_new, @@ -356,7 +356,7 @@ nv30_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv30_gr_new, @@ -377,7 +377,7 @@ nv31_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv30_gr_new, @@ -399,7 +399,7 @@ nv34_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv34_gr_new, @@ -421,7 +421,7 @@ nv35_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv35_gr_new, @@ -442,7 +442,7 @@ nv36_chipset = { .mc = nv04_mc_new, .mmu = nv04_mmu_new, .timer = nv04_timer_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv17_fifo_new, // .gr = nv35_gr_new, @@ -466,7 +466,7 @@ nv40_chipset = { .therm = nv40_therm_new, .timer = nv40_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -491,7 +491,7 @@ nv41_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -516,7 +516,7 @@ nv42_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -541,7 +541,7 @@ nv43_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -566,7 +566,7 @@ nv44_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -591,7 +591,7 @@ nv45_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -616,7 +616,7 @@ nv46_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -641,7 +641,7 @@ nv47_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -666,7 +666,7 @@ nv49_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -691,7 +691,7 @@ nv4a_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -716,7 +716,7 @@ nv4b_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -741,7 +741,7 @@ nv4c_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -766,7 +766,7 @@ nv4e_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -794,7 +794,7 @@ nv50_chipset = { .therm = nv50_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv50_disp_new, + .disp = nv50_disp_new, .dma = nv50_dma_new, // .fifo = nv50_fifo_new, // .gr = nv50_gr_new, @@ -819,7 +819,7 @@ nv63_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -844,7 +844,7 @@ nv67_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -869,7 +869,7 @@ nv68_chipset = { .therm = nv40_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = nv04_disp_new, + .disp = nv04_disp_new, .dma = nv04_dma_new, // .fifo = nv40_fifo_new, // .gr = nv40_gr_new, @@ -899,7 +899,7 @@ nv84_chipset = { .volt = nv40_volt_new, .bsp = g84_bsp_new, .cipher = g84_cipher_new, -// .disp = g84_disp_new, + .disp = g84_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -930,7 +930,7 @@ nv86_chipset = { .volt = nv40_volt_new, .bsp = g84_bsp_new, .cipher = g84_cipher_new, -// .disp = g84_disp_new, + .disp = g84_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -961,7 +961,7 @@ nv92_chipset = { .volt = nv40_volt_new, .bsp = g84_bsp_new, .cipher = g84_cipher_new, -// .disp = g84_disp_new, + .disp = g84_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -992,7 +992,7 @@ nv94_chipset = { .volt = nv40_volt_new, .bsp = g84_bsp_new, .cipher = g84_cipher_new, -// .disp = g94_disp_new, + .disp = g94_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -1029,7 +1029,7 @@ nv96_chipset = { .vp = g84_vp_new, .cipher = g84_cipher_new, .bsp = g84_bsp_new, -// .disp = g94_disp_new, + .disp = g94_disp_new, // .pm = g84_pm_new, }; @@ -1060,7 +1060,7 @@ nv98_chipset = { .sec = g98_sec_new, .msvld = g98_msvld_new, .msppp = g98_msppp_new, -// .disp = g94_disp_new, + .disp = g94_disp_new, // .pm = g84_pm_new, }; @@ -1085,7 +1085,7 @@ nva0_chipset = { .volt = nv40_volt_new, .bsp = g84_bsp_new, .cipher = g84_cipher_new, -// .disp = gt200_disp_new, + .disp = gt200_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -1116,7 +1116,7 @@ nva3_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, .ce[0] = gt215_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -1149,7 +1149,7 @@ nva5_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, .ce[0] = gt215_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -1181,7 +1181,7 @@ nva8_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, .ce[0] = gt215_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -1211,7 +1211,7 @@ nvaa_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = g94_disp_new, + .disp = g94_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -1242,7 +1242,7 @@ nvac_chipset = { .therm = g84_therm_new, .timer = nv41_timer_new, .volt = nv40_volt_new, -// .disp = g94_disp_new, + .disp = g94_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -1275,7 +1275,7 @@ nvaf_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, .ce[0] = gt215_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = nv50_dma_new, // .fifo = g84_fifo_new, // .gr = nv50_gr_new, @@ -1310,7 +1310,7 @@ nvc0_chipset = { .volt = nv40_volt_new, .ce[0] = gf100_ce_new, .ce[1] = gf100_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf100_gr_new, @@ -1344,7 +1344,7 @@ nvc1_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, .ce[0] = gf100_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf108_gr_new, @@ -1378,7 +1378,7 @@ nvc3_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, .ce[0] = gf100_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, @@ -1413,7 +1413,7 @@ nvc4_chipset = { .volt = nv40_volt_new, .ce[0] = gf100_ce_new, .ce[1] = gf100_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, @@ -1448,7 +1448,7 @@ nvc8_chipset = { .volt = nv40_volt_new, .ce[0] = gf100_ce_new, .ce[1] = gf100_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf110_gr_new, @@ -1483,7 +1483,7 @@ nvce_chipset = { .volt = nv40_volt_new, .ce[0] = gf100_ce_new, .ce[1] = gf100_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, @@ -1517,7 +1517,7 @@ nvcf_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, .ce[0] = gf100_ce_new, -// .disp = gt215_disp_new, + .disp = gt215_disp_new, .dma = gf100_dma_new, // .fifo = gf100_fifo_new, // .gr = gf104_gr_new, @@ -1549,7 +1549,7 @@ nvd7_chipset = { .therm = gf119_therm_new, .timer = nv41_timer_new, .ce[0] = gf100_ce_new, -// .disp = gf119_disp_new, + .disp = gf119_disp_new, .dma = gf119_dma_new, // .fifo = gf100_fifo_new, // .gr = gf117_gr_new, @@ -1583,7 +1583,7 @@ nvd9_chipset = { .timer = nv41_timer_new, .volt = nv40_volt_new, .ce[0] = gf100_ce_new, -// .disp = gf119_disp_new, + .disp = gf119_disp_new, .dma = gf119_dma_new, // .fifo = gf100_fifo_new, // .gr = gf119_gr_new, @@ -1619,7 +1619,7 @@ nve4_chipset = { .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, -// .disp = gk104_disp_new, + .disp = gk104_disp_new, .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk104_gr_new, @@ -1655,7 +1655,7 @@ nve6_chipset = { .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, -// .disp = gk104_disp_new, + .disp = gk104_disp_new, .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk104_gr_new, @@ -1691,7 +1691,7 @@ nve7_chipset = { .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, -// .disp = gk104_disp_new, + .disp = gk104_disp_new, .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk104_gr_new, @@ -1751,7 +1751,7 @@ nvf0_chipset = { .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, -// .disp = gk110_disp_new, + .disp = gk110_disp_new, .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk110_gr_new, @@ -1787,7 +1787,7 @@ nvf1_chipset = { .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, -// .disp = gk110_disp_new, + .disp = gk110_disp_new, .dma = gf119_dma_new, // .fifo = gk104_fifo_new, // .gr = gk110b_gr_new, @@ -1823,7 +1823,7 @@ nv106_chipset = { .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, -// .disp = gk110_disp_new, + .disp = gk110_disp_new, .dma = gf119_dma_new, // .fifo = gk208_fifo_new, // .gr = gk208_gr_new, @@ -1858,7 +1858,7 @@ nv108_chipset = { .ce[0] = gk104_ce_new, .ce[1] = gk104_ce_new, .ce[2] = gk104_ce_new, -// .disp = gk110_disp_new, + .disp = gk110_disp_new, .dma = gf119_dma_new, // .fifo = gk208_fifo_new, // .gr = gk208_gr_new, @@ -1891,7 +1891,7 @@ nv117_chipset = { .timer = gk20a_timer_new, .ce[0] = gk104_ce_new, .ce[2] = gk104_ce_new, -// .disp = gm107_disp_new, + .disp = gm107_disp_new, .dma = gf119_dma_new, // .fifo = gk208_fifo_new, // .gr = gm107_gr_new, @@ -1920,7 +1920,7 @@ nv124_chipset = { .ce[0] = gm204_ce_new, .ce[1] = gm204_ce_new, .ce[2] = gm204_ce_new, -// .disp = gm204_disp_new, + .disp = gm204_disp_new, .dma = gf119_dma_new, // .fifo = gm204_fifo_new, // .gr = gm204_gr_new, @@ -1949,7 +1949,7 @@ nv126_chipset = { .ce[0] = gm204_ce_new, .ce[1] = gm204_ce_new, .ce[2] = gm204_ce_new, -// .disp = gm204_disp_new, + .disp = gm204_disp_new, .dma = gf119_dma_new, // .fifo = gm204_fifo_new, // .gr = gm206_gr_new, |