#include <linux/export.h>

#include <linux/i2c.h>

#include <linux/notifier.h>

#include <linux/slab.h>

#include <linux/sort.h>

#include <linux/string_helpers.h>

#include "intel_vrr.h"

#include "intel_crtc_state_dump.h"

/* DP DSC throughput values used for slice count calculations KPixels/s */

#define DP_DSC_PEAK_PIXEL_RATE 2720000

#define DP_DSC_MAX_ENC_THROUGHPUT_0 340000

/* Constants for DP DSC configurations */

static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15};

*/

/**

* intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)

static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)

{

struct intel_connector *connector = intel_dp->attached_connector;

struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

struct intel_encoder *encoder = &intel_dig_port->base;

if (intel_dp->num_sink_rates)

return;

"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD with no link rates, using defaults\n",

connector->base.base.id, connector->base.name,

encoder->base.base.id, encoder->base.name);

static void intel_dp_set_max_sink_lane_count(struct intel_dp *intel_dp)

{

struct intel_connector *connector = intel_dp->attached_connector;

struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

struct intel_encoder *encoder = &intel_dig_port->base;

return;

}

"[CONNECTOR:%d:%s][ENCODER:%d:%s] Invalid DPCD max lane count (%d), using default\n",

connector->base.base.id, connector->base.name,

encoder->base.base.id, encoder->base.name,

int intel_dp_common_rate(struct intel_dp *intel_dp, int index)

{

index < 0 || index >= intel_dp->num_common_rates))

return 162000;

bool intel_dp_has_joiner(struct intel_dp *intel_dp)

{

struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

struct intel_encoder *encoder = &intel_dig_port->base;

/* eDP MSO is not compatible with joiner */

if (intel_dp->mso_link_count)

return false;

encoder->port != PORT_A);

}

static int mtl_max_source_rate(struct intel_dp *intel_dp)

{

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

if (intel_encoder_is_c10phy(encoder))

return 810000;

return 1350000;

return 2000000;

static const int g4x_rates[] = {

162000, 270000

};

const int *source_rates;

int size, max_rate = 0, vbt_max_rate;

/* This should only be done once */

intel_dp->source_rates || intel_dp->num_source_rates);

source_rates = bmg_rates;

size = ARRAY_SIZE(bmg_rates);

} else {

size = ARRAY_SIZE(mtl_rates);

}

max_rate = mtl_max_source_rate(intel_dp);

source_rates = icl_rates;

size = ARRAY_SIZE(icl_rates);

max_rate = dg2_max_source_rate(intel_dp);

max_rate = 810000;

max_rate = ehl_max_source_rate(intel_dp);

else

max_rate = icl_max_source_rate(intel_dp);

source_rates = bxt_rates;

size = ARRAY_SIZE(bxt_rates);

source_rates = skl_rates;

size = ARRAY_SIZE(skl_rates);

source_rates = hsw_rates;

size = ARRAY_SIZE(hsw_rates);

} else {

static void intel_dp_link_config_init(struct intel_dp *intel_dp)

{

struct intel_dp_link_config *lc;

int num_common_lane_configs;

int i;

int j;

return;

num_common_lane_configs = ilog2(intel_dp_max_common_lane_count(intel_dp)) + 1;

ARRAY_SIZE(intel_dp->link.configs)))

return;

void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count)

{

const struct intel_dp_link_config *lc;

idx = 0;

lc = &intel_dp->link.configs[idx];

static void intel_dp_set_common_rates(struct intel_dp *intel_dp)

{

!intel_dp->num_source_rates || !intel_dp->num_sink_rates);

intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,

intel_dp->common_rates);

/* Paranoia, there should always be something in common. */

intel_dp->common_rates[0] = 162000;

intel_dp->num_common_rates = 1;

}

}

static int

{

return 17280 * 8;

return 7680 * 8;

else

return 6144 * 8;

}

{

u32 bits_per_pixel = bpp;

int i;

/* Error out if the max bpp is less than smallest allowed valid bpp */

if (bits_per_pixel < valid_dsc_bpp[0]) {

bits_per_pixel, valid_dsc_bpp[0]);

return 0;

}

/* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */

bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1);

/*

* DSC enabled.

*/

if (bits_per_pixel < 8) {

bits_per_pixel);

return 0;

}

if (bits_per_pixel < valid_dsc_bpp[i + 1])

break;

}

bits_per_pixel, valid_dsc_bpp[i]);

bits_per_pixel = valid_dsc_bpp[i];

u32 mode_hdisplay,

int num_joined_pipes)

{

u32 max_bpp;

/* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */

max_bpp *= num_joined_pipes;

}

static

u32 mode_clock, u32 mode_hdisplay,

int num_joined_pipes)

{

u32 max_bpp = small_joiner_ram_max_bpp(display, mode_hdisplay, num_joined_pipes);

if (num_joined_pipes > 1)

return max_bpp;

}

u32 link_clock, u32 lane_count,

u32 mode_clock, u32 mode_hdisplay,

int num_joined_pipes,

if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420)

bits_per_pixel = min_t(u32, bits_per_pixel, 31);

"total bw %u pixel clock %u\n",

bits_per_pixel, timeslots,

(link_clock * lane_count * 8),

intel_dp_mode_to_fec_clock(mode_clock));

mode_hdisplay, num_joined_pipes);

bits_per_pixel = min(bits_per_pixel, joiner_max_bpp);

return bits_per_pixel;

}

int mode_clock, int mode_hdisplay,

int num_joined_pipes)

{

u8 min_slice_count, i;

int max_slice_width;

* Due to some DSC engine BW limitations, we need to enable second

* slice and VDSC engine, whenever we approach close enough to max CDCLK

*/

min_slice_count = max_t(u8, min_slice_count, 2);

max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd);

if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) {

"Unsupported slice width %d by DP DSC Sink device\n",

max_slice_width);

return 0;

for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) {

u8 test_slice_count = valid_dsc_slicecount[i] * num_joined_pipes;

if (test_slice_count >

drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false))

break;

if (num_joined_pipes > 1 && valid_dsc_slicecount[i] < 2)

continue;

if (min_slice_count <= test_slice_count)

return test_slice_count;

}

min_slice_count);

return 0;

}

static bool source_can_output(struct intel_dp *intel_dp,

enum intel_output_format format)

{

switch (format) {

case INTEL_OUTPUT_FORMAT_RGB:

/*

* No YCbCr output support on gmch platforms.

* Also, ILK doesn't seem capable of DP YCbCr output.

*/

case INTEL_OUTPUT_FORMAT_YCBCR420:

/* Platform < Gen 11 cannot output YCbCr420 format */

default:

MISSING_CASE(format);

intel_dp_output_format(struct intel_connector *connector,

enum intel_output_format sink_format)

{

struct intel_dp *intel_dp = intel_attached_dp(connector);

enum intel_output_format force_dsc_output_format =

intel_dp->force_dsc_output_format;

enum intel_output_format output_format;

dfp_can_convert(intel_dp, force_dsc_output_format, sink_format)))

return force_dsc_output_format;

}

if (sink_format == INTEL_OUTPUT_FORMAT_RGB ||

else

output_format = INTEL_OUTPUT_FORMAT_YCBCR420;

return output_format;

}

return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format));

}

int hdisplay)

{

/*

*

* TODO: confirm the behaviour on HSW+

*/

}

static int intel_dp_max_tmds_clock(struct intel_dp *intel_dp)

int hdisplay, int clock,

int num_joined_pipes)

{

int hdisplay_limit;

if (!intel_dp_has_joiner(intel_dp))

num_joined_pipes /= 2;

hdisplay > num_joined_pipes * hdisplay_limit;

}

int hdisplay, int clock)

{

struct intel_display *display = to_intel_display(intel_dp);

if (connector->force_joined_pipes)

return connector->force_joined_pipes;

intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 4))

return 4;

intel_dp_needs_joiner(intel_dp, connector, hdisplay, clock, 2))

return 2;

bool intel_dp_has_dsc(const struct intel_connector *connector)

{

return false;

return false;

if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&

static enum drm_mode_status

intel_dp_mode_valid(struct drm_connector *_connector,

{

struct intel_connector *connector = to_intel_connector(_connector);

struct intel_dp *intel_dp = intel_attached_dp(connector);

const struct drm_display_mode *fixed_mode;

int target_clock = mode->clock;

int max_rate, mode_rate, max_lanes, max_link_clock;

u16 dsc_max_compressed_bpp = 0;

u8 dsc_slice_count = 0;

enum drm_mode_status status;

bool dsc = false;

int num_joined_pipes;

if (status != MODE_OK)

return status;

if (target_clock > max_dotclk)

return MODE_CLOCK_HIGH;

return MODE_H_ILLEGAL;

max_link_clock = intel_dp_max_link_rate(intel_dp);

true);

} else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) {

dsc_max_compressed_bpp =

max_link_clock,

max_lanes,

target_clock,

dsc = dsc_max_compressed_bpp && dsc_slice_count;

}

return MODE_CLOCK_HIGH;

if (mode_rate > max_rate && !dsc)

if (status != MODE_OK)

return status;

}

{

}

{

}

{

int i;

}

static void intel_dp_print_rates(struct intel_dp *intel_dp)

{

if (!drm_debug_enabled(DRM_UT_KMS))

return;

}

static int forced_link_rate(struct intel_dp *intel_dp)

int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)

{

int i = intel_dp_rate_index(intel_dp->sink_rates,

intel_dp->num_sink_rates, rate);

i = 0;

return i;

static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,

const struct intel_crtc_state *pipe_config)

{

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

return true;

!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))

return true;

drm_dp_sink_supports_fec(connector->dp.fec_capability);

}

const struct intel_crtc_state *crtc_state)

{

if (!intel_dp_has_dsc(connector))

return false;

return false;

return intel_dsc_source_support(crtc_state);

const struct intel_crtc_state *crtc_state,

bool respect_downstream_limits)

{

int bpp, bpc;

bpc = crtc_state->pipe_bpp / 3;

bpp = bpc * 3;

if (intel_dp_is_edp(intel_dp)) {

/* Get bpp from vbt only for panels that dont have bpp in edid */

"clamping bpp for eDP panel to BIOS-provided %i\n",

}

}

static bool has_seamless_m_n(struct intel_connector *connector)

{

/*

* Seamless M/N reprogramming only implemented

* for BDW+ double buffered M/N registers so far.

*/

intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS;

}

return -EINVAL;

}

{

/* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */

return 12;

return 10;

}

int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector,

u8 max_req_bpc)

{

int i, num_bpc;

u8 dsc_bpc[3] = {};

if (!dsc_max_bpc)

return dsc_max_bpc;

num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,

dsc_bpc);

return 0;

}

{

}

static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])

static int intel_dp_dsc_compute_params(const struct intel_connector *connector,

struct intel_crtc_state *crtc_state)

{

struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;

int ret;

(connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &

DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;

vdsc_cfg->dsc_version_minor =

intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd));

if (vdsc_cfg->convert_rgb)

vdsc_cfg->convert_rgb =

vdsc_cfg->line_buf_depth = min(INTEL_DP_DSC_MAX_LINE_BUF_DEPTH,

drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd));

if (!vdsc_cfg->line_buf_depth) {

"DSC Sink Line Buffer Depth invalid\n");

return -EINVAL;

}

static bool intel_dp_dsc_supports_format(const struct intel_connector *connector,

enum intel_output_format output_format)

{

u8 sink_dsc_format;

switch (output_format) {

sink_dsc_format = DP_DSC_YCbCr444;

break;

case INTEL_OUTPUT_FORMAT_YCBCR420:

intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2)

return false;

sink_dsc_format = DP_DSC_YCbCr420_Native;

return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format);

}

u32 lane_count, u32 mode_clock,

enum intel_output_format output_format,

int timeslots)

u32 available_bw, required_bw;

available_bw = (link_clock * lane_count * timeslots * 16) / 8;

return available_bw > required_bw;

}

static int dsc_compute_link_config(struct intel_dp *intel_dp,

struct intel_crtc_state *pipe_config,

int timeslots)

{

const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;

for (lane_count = limits->min_lane_count;

lane_count <= limits->max_lane_count;

lane_count <<= 1) {

pipe_config->lane_count = lane_count;

pipe_config->port_clock = link_rate;

return 0;

}

}

static

u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector,

int bpc)

{

u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd);

return 0;

}

{

/* From Mandatory bit rate range Support Table 2-157 (DP v2.0) */

switch (pipe_config->output_format) {

}

int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector,

int bpc)

{

return intel_dp_dsc_max_sink_compressed_bppx16(connector,

static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp)

{

/*

* Max Compressed bpp for Gen 13+ is 27bpp.

* For earlier platform is 23bpp. (Bspec:49259).

*/

return 23;

else

return 27;

}

/*

*/

{

}

}

/*

*/

int ret;

/* Compressed BPP should be less than the Input DSC bpp */

continue;

ret = dsc_compute_link_config(intel_dp,

pipe_config,

limits,

timeslots);

if (ret == 0) {

if (intel_dp->force_dsc_fractional_bpp_en &&

return 0;

}

}

}

{

/* Min DSC Input BPC for ICL+ is 8 */

}

static

int pipe_bpp)

{

}

static

int intel_dp_force_dsc_pipe_bpp(struct intel_dp *intel_dp,

{

int forced_bpp;

if (!intel_dp->force_dsc_bpc)

forced_bpp = intel_dp->force_dsc_bpc * 3;

return forced_bpp;

}

intel_dp->force_dsc_bpc);

return 0;

static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,

struct intel_crtc_state *pipe_config,

struct drm_connector_state *conn_state,

int timeslots)

{

const struct intel_connector *connector =

to_intel_connector(conn_state->connector);

u8 dsc_bpc[3] = {};

int forced_bpp, pipe_bpp;

int num_bpc, i, ret;

if (forced_bpp) {

limits, forced_bpp, timeslots);

if (ret == 0) {

pipe_config->pipe_bpp = forced_bpp;

}

}

/*

* Get the maximum DSC bpc that will be supported by any valid

* link configuration and compressed bpp.

num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc);

for (i = 0; i < num_bpc; i++) {

pipe_bpp = dsc_bpc[i] * 3;

continue;

limits, pipe_bpp, timeslots);

if (ret == 0) {

pipe_config->pipe_bpp = pipe_bpp;

static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,

struct intel_crtc_state *pipe_config,

struct drm_connector_state *conn_state,

{

struct intel_connector *connector =

to_intel_connector(conn_state->connector);

int pipe_bpp, forced_bpp;

if (forced_bpp) {

pipe_bpp = forced_bpp;

} else {

/* For eDP use max bpp that can be supported with DSC. */

pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc);

"Computed BPC is not in DSC BPC limits\n");

return -EINVAL;

}

pipe_config->port_clock = limits->max_rate;

pipe_config->lane_count = limits->max_lane_count;

/* Compressed BPP should be less than the Input DSC bpp */

dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);

return 0;

}

int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,

struct intel_crtc_state *pipe_config,

struct drm_connector_state *conn_state,

{

const struct intel_connector *connector =

to_intel_connector(conn_state->connector);

const struct drm_display_mode *adjusted_mode =

&pipe_config->hw.adjusted_mode;

int num_joined_pipes = intel_crtc_num_joined_pipes(pipe_config);

int ret;

if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format))

return -EINVAL;

/*

*/

if (intel_dp_is_edp(intel_dp))

ret = intel_edp_dsc_compute_pipe_bpp(intel_dp, pipe_config,

conn_state, limits);

ret = intel_dp_dsc_compute_pipe_bpp(intel_dp, pipe_config,

conn_state, limits, timeslots);

if (ret) {

"No Valid pipe bpp for given mode ret = %d\n", ret);

return ret;

}

drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd,

true);

if (!pipe_config->dsc.slice_count) {

pipe_config->dsc.slice_count);

return -EINVAL;

}

adjusted_mode->crtc_hdisplay,

num_joined_pipes);

if (!dsc_dp_slice_count) {

"Compressed Slice Count not supported\n");

return -EINVAL;

}

* VDSC engine operates at 1 Pixel per clock, so if peak pixel rate

* is greater than the maximum Cdclock and if slice count is even

* then we need to use 2 VDSC instances.

*/

ret = intel_dp_dsc_compute_params(connector, pipe_config);

if (ret < 0) {

"Cannot compute valid DSC parameters for Input Bpp = %d"

"Compressed BPP = " FXP_Q4_FMT "\n",

pipe_config->pipe_bpp,

}

pipe_config->dsc.compression_enable = true;

"Compressed Bpp = " FXP_Q4_FMT " Slice Count = %d\n",

pipe_config->pipe_bpp,

FXP_Q4_ARGS(pipe_config->dsc.compressed_bpp_x16),

return 0;

}

*/

intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,

const struct intel_crtc_state *crtc_state,

bool dsc,

struct link_config_limits *limits)

{

const struct drm_display_mode *adjusted_mode =

&crtc_state->hw.adjusted_mode;

const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

limits->link.min_bpp_x16 = fxp_q4_from_int(limits->pipe.min_bpp);

} else {

}

limits->link.max_bpp_x16 = max_link_bpp_x16;

"[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp " FXP_Q4_FMT "\n",

encoder->base.base.id, encoder->base.name,

crtc->base.base.id, crtc->base.name,

return true;

}

intel_dp_compute_config_limits(struct intel_dp *intel_dp,

struct intel_crtc_state *crtc_state,

bool respect_downstream_limits,

bool dsc,

struct link_config_limits *limits)

{

limits->min_rate = intel_dp_min_link_rate(intel_dp);

limits->max_rate = intel_dp_max_link_rate(intel_dp);

limits->min_rate = min(limits->min_rate, limits->max_rate);

limits->min_lane_count = intel_dp_min_lane_count(intel_dp);

limits->max_lane_count = intel_dp_max_lane_count(intel_dp);

limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);

/*

* Use the maximum clock and number of lanes the eDP panel

* advertizes being capable of in case the initial fast

* optimal params failed us. The panels are generally

intel_dp_test_compute_config(intel_dp, crtc_state, limits);

return intel_dp_compute_config_link_bpp_limits(intel_dp,

crtc_state,

dsc,

limits);

return intel_dp_link_required(adjusted_mode->crtc_clock, bpp);

}

int num_joined_pipes)

{

/*

* compression.

* Ultrajoiner always needs compression.

*/

num_joined_pipes == 4;

}

struct drm_connector_state *conn_state,

bool respect_downstream_limits)

{

struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);

struct intel_connector *connector =

to_intel_connector(conn_state->connector);

if (num_joined_pipes > 1)

pipe_config->joiner_pipes = GENMASK(crtc->pipe + num_joined_pipes - 1, crtc->pipe);

dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||

!intel_dp_compute_config_limits(intel_dp, pipe_config,

*/

ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,

conn_state, &limits);

if (ret)

dsc_needed = true;

}

if (dsc_needed) {

str_yes_no(ret), str_yes_no(joiner_needs_dsc),

str_yes_no(intel_dp->force_dsc_en));

return -EINVAL;

ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,

if (ret < 0)

return ret;

}

"DP lane count %d clock %d bpp input %d compressed " FXP_Q4_FMT " link rate required %d available %d\n",

pipe_config->lane_count, pipe_config->port_clock,

pipe_config->pipe_bpp,

}

}

{

return false;

return false;

return true;

const struct drm_connector_state *conn_state,

struct drm_dp_vsc_sdp *vsc)

{

if (crtc_state->has_panel_replay) {

/*

vsc->bpc = crtc_state->pipe_bpp / 3;

/* only RGB pixelformat supports 6 bpc */

vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB);

/* all YCbCr are always limited range */

crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_ADAPTIVE_SYNC);

as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;

as_sdp->length = 0x9;

as_sdp->duration_incr_ms = 0;

if (crtc_state->cmrr.enable) {

as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;

as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);

as_sdp->target_rr_divider = true;

} else {

as_sdp->target_rr = 0;

}

}

struct intel_crtc_state *crtc_state,

const struct drm_connector_state *conn_state)

{

int ret;

struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm;

if (!conn_state->hdr_output_metadata)

ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state);

if (ret) {

return;

}

const struct intel_crtc_state *pipe_config,

const struct drm_display_mode *downclock_mode)

{

if (pipe_config->vrr.enable)

return false;

if (pipe_config->has_pch_encoder)

return false;

return false;

return downclock_mode &&

struct intel_crtc_state *pipe_config,

int link_bpp_x16)

{

const struct drm_display_mode *downclock_mode =

intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);

int pixel_clock;

pipe_config->update_m_n = true;

if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {

intel_zero_m_n(&pipe_config->dp_m2_n2);

return;

}

pipe_config->msa_timing_delay = connector->panel.vbt.edp.drrs_msa_timing_delay;

pipe_config->has_drrs = true;

static bool intel_dp_has_audio(struct intel_encoder *encoder,

const struct drm_connector_state *conn_state)

{

const struct intel_digital_connector_state *intel_conn_state =

to_intel_digital_connector_state(conn_state);

struct intel_connector *connector =

to_intel_connector(conn_state->connector);

return false;

if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)

struct drm_connector_state *conn_state,

bool respect_downstream_limits)

{

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

struct intel_connector *connector = intel_dp->attached_connector;

const struct drm_display_info *info = &connector->base.display_info;

ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);

if (ycbcr_420_only && !connector->base.ycbcr_420_allowed) {

"YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");

crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;

} else {

intel_dp_is_uhbr(pipe_config);

}

void

intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state,

struct intel_encoder *encoder,

intel_dp->needs_modeset_retry = true;

if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {

return;

}

if (!conn_state->base.crtc)

continue;

}

}

struct intel_crtc_state *pipe_config,

struct drm_connector_state *conn_state)

{

struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);

struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

struct intel_connector *connector = intel_dp->attached_connector;

int ret = 0, link_bpp_x16;

fixed_mode = intel_panel_fixed_mode(connector, adjusted_mode);

if (intel_dp_is_edp(intel_dp) && fixed_mode) {

ret = intel_panel_compute_config(connector, adjusted_mode);

if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)

return -EINVAL;

return -EINVAL;

/*

if ((intel_dp_is_edp(intel_dp) && fixed_mode) ||

pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {

if (ret)

return ret;

}

pipe_config->limited_color_range =

intel_dp_limited_color_range(pipe_config, conn_state);

if (pipe_config->dsc.compression_enable)

link_bpp_x16 = pipe_config->dsc.compressed_bpp_x16;

pipe_config->splitter.link_count = n;

pipe_config->splitter.pixel_overlap = overlap;

n, overlap);

adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap;

intel_dp_audio_compute_config(encoder, pipe_config, conn_state);

/* FIXME: abstract this better */

if (pipe_config->splitter.enable)

pipe_config->dp_m_n.data_m *= pipe_config->splitter.link_count;

intel_vrr_compute_config(pipe_config, conn_state);

intel_dp_compute_as_sdp(intel_dp, pipe_config);

intel_psr_compute_config(intel_dp, pipe_config, conn_state);

void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,

const struct drm_connector_state *conn_state)

{

struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder));

if (!intel_dp_is_edp(intel_dp))

return;

intel_backlight_enable(crtc_state, conn_state);

intel_pps_backlight_on(intel_dp);

void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state)

{

struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder));

if (!intel_dp_is_edp(intel_dp))

return;

intel_pps_backlight_off(intel_dp);

intel_backlight_disable(old_conn_state);

intel_dp_sink_set_dsc_decompression(struct intel_connector *connector,

bool enable)

{

if (write_dsc_decompression_flag(connector->dp.dsc_decompression_aux,

DP_DECOMPRESSION_EN, enable) < 0)

"Failed to %s sink decompression state\n",

str_enable_disable(enable));

}

intel_dp_sink_set_dsc_passthrough(const struct intel_connector *connector,

bool enable)

{

if (!aux)

return;

if (write_dsc_decompression_flag(aux,

DP_DSC_PASSTHROUGH_EN, enable) < 0)

"Failed to %s sink compression passthrough state\n",

str_enable_disable(enable));

}

const struct intel_connector *connector,

bool for_get_ref)

{

struct drm_connector *_connector_iter;

struct drm_connector_state *old_conn_state;

struct drm_connector_state *new_conn_state;

* On SST the decompression AUX device won't be shared, each connector

* uses for this its own AUX targeting the sink device.

*/

return connector->dp.dsc_decompression_enabled ? 1 : 0;

for_each_oldnew_connector_in_state(&state->base, _connector_iter,

const struct intel_connector *

connector_iter = to_intel_connector(_connector_iter);

continue;

if (!connector_iter->dp.dsc_decompression_enabled)

continue;

(for_get_ref && !new_conn_state->crtc) ||

(!for_get_ref && !old_conn_state->crtc));

struct intel_connector *connector,

const struct intel_crtc_state *new_crtc_state)

{

if (!new_crtc_state->dsc.compression_enable)

return;

!connector->dp.dsc_decompression_aux ||

connector->dp.dsc_decompression_enabled))

return;

struct intel_connector *connector,

const struct intel_crtc_state *old_crtc_state)

{

if (!old_crtc_state->dsc.compression_enable)

return;

!connector->dp.dsc_decompression_aux ||

!connector->dp.dsc_decompression_enabled))

return;

static void

intel_dp_init_source_oui(struct intel_dp *intel_dp)

{

u8 oui[] = { 0x00, 0xaa, 0x01 };

u8 buf[3] = {};

* already set to what we want, so as to avoid clearing any state by accident

*/

if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0)

if (memcmp(oui, buf, sizeof(oui)) == 0) {

/* Assume the OUI was written now. */

}

if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) {

WRITE_ONCE(intel_dp->oui_valid, false);

}

void intel_dp_wait_source_oui(struct intel_dp *intel_dp)

{

struct intel_connector *connector = intel_dp->attached_connector;

connector->base.base.id, connector->base.name,

connector->panel.vbt.backlight.hdr_dpcd_refresh_timeout);

/* If the device supports it, try to set the power state appropriately */

void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode)

{

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

int ret, i;

/* Should have a valid DPCD by this point */

ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode);

} else {

/* Write the source OUI as early as possible */

intel_dp_init_source_oui(intel_dp);

msleep(1);

}

}

if (ret != 1)

encoder->base.base.id, encoder->base.name,

mode == DP_SET_POWER_D0 ? "D0" : "D3");

}

bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,

struct intel_crtc_state *crtc_state)

{

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

bool fastset = true;

*/

if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates,

crtc_state->port_clock) < 0) {

encoder->base.base.id, encoder->base.name);

crtc_state->uapi.connectors_changed = true;

fastset = false;

* Remove once we have readout for DSC.

*/

if (crtc_state->dsc.compression_enable) {

encoder->base.base.id, encoder->base.name);

crtc_state->uapi.mode_changed = true;

fastset = false;

}

if (CAN_PANEL_REPLAY(intel_dp)) {

"[ENCODER:%d:%s] Forcing full modeset to compute panel replay state\n",

encoder->base.base.id, encoder->base.name);

crtc_state->uapi.mode_changed = true;

static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp)

{

/* Clear the cached register set to avoid using stale values */

if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER,

intel_dp->pcon_dsc_dpcd,

sizeof(intel_dp->pcon_dsc_dpcd)) < 0)

DP_PCON_DSC_ENCODER);

(int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd);

}

static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp)

{

int max_frl_rate;

int max_lanes, rate_per_lane;

int max_dsc_lanes, dsc_rate_per_lane;

max_frl_rate = max_lanes * rate_per_lane;

if (max_dsc_lanes && dsc_rate_per_lane)

max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane);

}

static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp)

{

#define TIMEOUT_FRL_READY_MS 500

#define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000

int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret;

u8 max_frl_bw_mask = 0, frl_trained_mask;

bool is_active;

max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw;

max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp);

max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw);

return -EINVAL;

max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw);

if (intel_dp_pcon_is_frl_trained(intel_dp, max_frl_bw_mask, &frl_trained_mask))

goto frl_trained;

return -ETIMEDOUT;

frl_trained:

intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask);

intel_dp->frl.is_trained = true;

return 0;

}

void intel_dp_check_frl_training(struct intel_dp *intel_dp)

{

/*

* Always go for FRL training if:

if (intel_dp_pcon_start_frl_training(intel_dp) < 0) {

int ret, mode;

ret = intel_dp_pcon_set_tmds_mode(intel_dp);

mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL);

if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS)

} else {

}

}

intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp,

const struct intel_crtc_state *crtc_state)

{

int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd);

int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd);

const struct intel_crtc_state *crtc_state,

int num_slices, int slice_width)

{

int output_format = crtc_state->output_format;

int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd);

int hdmi_max_chunk_bytes =

return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width,

num_slices, output_format, hdmi_all_bpp,

intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp,

const struct intel_crtc_state *crtc_state)

{

u8 pps_param[6];

int slice_height;

int slice_width;

int num_slices;

int bits_per_pixel;

int ret;

bool hdmi_is_dsc_1_2;

if (!intel_dp_is_hdmi_2_1_sink(intel_dp))

return;

return;

if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) ||

!hdmi_is_dsc_1_2)

ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param);

if (ret < 0)

}

void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp,

const struct intel_crtc_state *crtc_state)

{

bool ycbcr444_to_420 = false;

bool rgb_to_ycbcr = false;

u8 tmp;

if (drm_dp_dpcd_writeb(&intel_dp->aux,

DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1)

str_enable_disable(intel_dp_has_hdmi_sink(intel_dp)));

if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) {

if (drm_dp_dpcd_writeb(&intel_dp->aux,

DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1)

"Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n",

str_enable_disable(intel_dp->dfp.ycbcr_444_to_420));

tmp = rgb_to_ycbcr ? DP_CONVERSION_BT709_RGB_YCBCR_ENABLE : 0;

if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0)

"Failed to %s protocol converter RGB->YCbCr conversion mode\n",

str_enable_disable(tmp));

}

void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector)

{

/*

* Clear the cached register set to avoid using stale values

if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY,

&connector->dp.fec_capability) < 0) {

return;

}

connector->dp.fec_capability);

}

static void

intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector)

{

/* Read DP Sink DSC Cap DPCD regs for DP v1.4 */

return;

if (intel_dp_is_edp(intel_dp))

static void intel_edp_mso_mode_fixup(struct intel_connector *connector,

struct drm_display_mode *mode)

{

struct intel_dp *intel_dp = intel_attached_dp(connector);

int n = intel_dp->mso_link_count;

int overlap = intel_dp->mso_pixel_overlap;

drm_mode_set_name(mode);

"[CONNECTOR:%d:%s] using generated MSO mode: " DRM_MODE_FMT "\n",

connector->base.base.id, connector->base.name,

DRM_MODE_ARG(mode));

void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp)

{

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

struct intel_connector *connector = intel_dp->attached_connector;

* up by the BIOS, and thus we can't get the mode at module

* load.

*/

"pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",

pipe_bpp, connector->panel.vbt.edp.bpp);

connector->panel.vbt.edp.bpp = pipe_bpp;

static void intel_edp_mso_init(struct intel_dp *intel_dp)

{

struct intel_connector *connector = intel_dp->attached_connector;

struct drm_display_info *info = &connector->base.display_info;

u8 mso;

return;

if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) {

return;

}

/* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */

mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK;

if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) {

mso = 0;

}

if (mso) {

mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso,

info->mso_pixel_overlap);

mso = 0;

}

}

static bool

intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector)

{

/* this function is meant to be called only once */

if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)

return false;

if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,

intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==

sizeof(intel_dp->edp_dpcd)) {

(int)sizeof(intel_dp->edp_dpcd),

intel_dp->edp_dpcd);

intel_dp_mst_mode_choose(struct intel_dp *intel_dp,

enum drm_dp_mst_mode sink_mst_mode)

{

return DRM_DP_SST;

if (!intel_dp_mst_source_support(intel_dp))

static enum drm_dp_mst_mode

intel_dp_mst_detect(struct intel_dp *intel_dp)

{

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

enum drm_dp_mst_mode sink_mst_mode;

enum drm_dp_mst_mode mst_detect;

mst_detect = intel_dp_mst_mode_choose(intel_dp, sink_mst_mode);

"[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s -> enable: %s\n",

encoder->base.base.id, encoder->base.name,

str_yes_no(intel_dp_mst_source_support(intel_dp)),

intel_dp_mst_mode_str(sink_mst_mode),

intel_dp_mst_mode_str(mst_detect));

return mst_detect;

if (intel_dp->is_mst)

intel_dp_mst_prepare_probe(intel_dp);

/* Avoid stale info on the next detect cycle. */

intel_dp->mst_detect = DRM_DP_SST;

static void

intel_dp_mst_disconnect(struct intel_dp *intel_dp)

{

if (!intel_dp->is_mst)

return;

intel_dp->is_mst = false;

}

static bool

}

static ssize_t

const struct hdmi_drm_infoframe *drm_infoframe,

struct dp_sdp *sdp,

size_t size)

len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf));

if (len < 0) {

return -ENOSPC;

}

if (len != infoframe_size) {

return -ENOSPC;

}

const struct intel_crtc_state *crtc_state,

unsigned int type)

{

struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

struct dp_sdp sdp = {};

ssize_t len;

len = drm_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp);

break;

case HDMI_PACKET_TYPE_GAMUT_METADATA:

&crtc_state->infoframes.drm.drm,

&sdp, sizeof(sdp));

break;

return;

}

return;

dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len);

const struct intel_crtc_state *crtc_state,

const struct drm_connector_state *conn_state)

{

u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW |

VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW |

VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK;

dip_enable |= VIDEO_DIP_ENABLE_AS_ADL;

/* TODO: Sanitize DSC enabling wrt. intel_dsc_dp_pps_write(). */

val &= ~VDIP_ENABLE_PPS;

/*

if (!enable || !crtc_state->has_psr)

val &= ~VIDEO_DIP_ENABLE_VSC_HSW;

if (!enable)

return;

struct intel_crtc_state *crtc_state,

struct drm_dp_as_sdp *as_sdp)

{

struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

unsigned int type = DP_SDP_ADAPTIVE_SYNC;

struct dp_sdp sdp = {};

int ret;

ret = intel_dp_as_sdp_unpack(as_sdp, &sdp, sizeof(sdp));

if (ret)

}

static int

struct intel_crtc_state *crtc_state,

struct drm_dp_vsc_sdp *vsc)

{

struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

unsigned int type = DP_SDP_VSC;

struct dp_sdp sdp = {};

int ret;

ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp));

if (ret)

}

static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder,

struct intel_crtc_state *crtc_state,

struct hdmi_drm_infoframe *drm_infoframe)

{

struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA;

struct dp_sdp sdp = {};

int ret;

sizeof(sdp));

if (ret)

"Failed to unpack DP HDR Metadata Infoframe SDP\n");

}

static bool intel_dp_link_ok(struct intel_dp *intel_dp,

u8 link_status[DP_LINK_STATUS_SIZE])

{

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

bool uhbr = intel_dp->link_rate >= 1000000;

bool ok;

return true;

intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status);

"[ENCODER:%d:%s] %s link not ok, retraining\n",

encoder->base.base.id, encoder->base.name,

uhbr ? "128b/132b" : "8b/10b");

{

bool handled = false;

if (esi[1] & DP_CP_IRQ) {

intel_hdcp_handle_cp_irq(intel_dp->attached_connector);

static bool intel_dp_mst_link_status(struct intel_dp *intel_dp)

{

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

u8 link_status[DP_LINK_STATUS_SIZE] = {};

const size_t esi_link_status_size = DP_LINK_STATUS_SIZE - 2;

if (drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS_ESI, link_status,

esi_link_status_size) != esi_link_status_size) {

"[ENCODER:%d:%s] Failed to read link status\n",

encoder->base.base.id, encoder->base.name);

return false;

static bool

intel_dp_check_mst_status(struct intel_dp *intel_dp)

{

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

struct intel_encoder *encoder = &dig_port->base;

bool link_ok = true;

bool reprobe_needed = false;

for (;;) {

u8 esi[4] = {};

u8 ack[4] = {};

if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) {

"failed to get ESI - device may have failed\n");

link_ok = false;

break;

}

esi[3] & LINK_STATUS_CHANGED) {

if (!intel_dp_mst_link_status(intel_dp))

link_ok = false;

intel_dp_mst_hpd_irq(intel_dp, esi, ack);

if (esi[3] & DP_TUNNELING_IRQ) {

&intel_dp->aux))

reprobe_needed = true;

ack[3] |= DP_TUNNELING_IRQ;

break;

if (!intel_dp_ack_sink_irq_esi(intel_dp, ack))

if (ack[1] & (DP_DOWN_REP_MSG_RDY | DP_UP_REQ_MSG_RDY))

}

if (!link_ok || intel_dp->link.force_retrain)

bool intel_dp_has_connector(struct intel_dp *intel_dp,

const struct drm_connector_state *conn_state)

{

struct intel_encoder *encoder;

enum pipe pipe;

return true;

/* MST */

if (conn_state->best_encoder == &encoder->base)

return true;

}

struct drm_modeset_acquire_ctx *ctx,

u8 *pipe_mask)

{

struct drm_connector_list_iter conn_iter;

struct intel_connector *connector;

int ret = 0;

*pipe_mask = 0;

for_each_intel_connector_iter(connector, &conn_iter) {

struct drm_connector_state *conn_state =

connector->base.state;

crtc_state = to_intel_crtc_state(crtc->base.state);

if (!crtc_state->hw.active)

continue;

static int intel_dp_retrain_link(struct intel_encoder *encoder,

struct drm_modeset_acquire_ctx *ctx)

{

struct intel_dp *intel_dp = enc_to_intel_dp(encoder);

u8 pipe_mask;

int ret;

if (!intel_dp_is_connected(intel_dp))

return 0;

ctx);

if (ret)

return ret;

if (!intel_dp_needs_link_retrain(intel_dp))

return 0;

encoder->base.base.id, encoder->base.name,

str_yes_no(intel_dp->link.force_retrain));

if (ret == -EDEADLK)

return ret;

intel_dp->link.force_retrain = false;

if (ret)

"[ENCODER:%d:%s] link retraining failed: %pe\n",

encoder->base.base.id, encoder->base.name,

ERR_PTR(ret));

static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp)

{

u8 val;

if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)

intel_hdcp_handle_cp_irq(intel_dp->attached_connector);

if (val & DP_SINK_SPECIFIC_IRQ)

}

static bool intel_dp_check_link_service_irq(struct intel_dp *intel_dp)

{

bool reprobe_needed = false;

u8 val;

return false;

if ((val & DP_TUNNELING_IRQ) &&

&intel_dp->aux))

reprobe_needed = true;

static enum drm_connector_status

intel_dp_detect_dpcd(struct intel_dp *intel_dp)

{

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

u8 *dpcd = intel_dp->dpcd;

u8 type;

return connector_status_connected;

if (!intel_dp_get_dpcd(intel_dp))

return connector_status_disconnected;

}

/* Anything else is out of spec, warn and ignore */

return connector_status_disconnected;

}

*/

bool intel_digital_port_connected_locked(struct intel_encoder *encoder)

{

struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

bool is_glitch_free = intel_tc_port_handles_hpd_glitches(dig_port);

bool is_connected = false;

intel_wakeref_t wakeref;

unsigned long wait_expires = jiffies + msecs_to_jiffies_timeout(4);

do {

intel_dp_update_dfp(struct intel_dp *intel_dp,

const struct drm_edid *drm_edid)

{

struct intel_connector *connector = intel_dp->attached_connector;

intel_dp->dfp.max_bpc =

drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd,

intel_dp->downstream_ports);

"[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n",

connector->base.base.id, connector->base.name,

intel_dp->dfp.max_bpc,

static void

intel_dp_update_420(struct intel_dp *intel_dp)

{

struct intel_connector *connector = intel_dp->attached_connector;

intel_dp->dfp.ycbcr420_passthrough =

intel_dp->downstream_ports);

/* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */

intel_dp->dfp.ycbcr_444_to_420 =

drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd,

intel_dp->downstream_ports);

intel_dp->dfp.rgb_to_ycbcr =

connector->base.ycbcr_420_allowed = intel_dp_can_ycbcr420(intel_dp);

"[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n",

connector->base.base.id, connector->base.name,

str_yes_no(intel_dp->dfp.rgb_to_ycbcr),

static void

intel_dp_set_edid(struct intel_dp *intel_dp)

{

struct intel_connector *connector = intel_dp->attached_connector;

const struct drm_edid *drm_edid;

bool vrr_capable;

drm_edid_connector_update(&connector->base, drm_edid);

vrr_capable = intel_vrr_is_capable(connector);

connector->base.base.id, connector->base.name, str_yes_no(vrr_capable));

drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);

static void

intel_dp_detect_sdp_caps(struct intel_dp *intel_dp)

{

drm_dp_as_sdp_supported(&intel_dp->aux, intel_dp->dpcd);

}

static int

struct drm_modeset_acquire_ctx *ctx,

bool force)

{

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

struct intel_encoder *encoder = &dig_port->base;

enum drm_connector_status status;

int ret;

return connector_status_disconnected;

intel_pps_vdd_on(intel_dp);

if (status == connector_status_disconnected) {

intel_dp_test_reset(intel_dp);

intel_dp->psr.sink_panel_replay_support = false;

intel_dp->psr.sink_panel_replay_su_support = false;

}

if (ret == 1)

if (!intel_dp_is_edp(intel_dp))

intel_psr_init_dpcd(intel_dp);

intel_dp_detect_sdp_caps(intel_dp);

intel_dp->aux.i2c_defer_count = 0;

intel_dp_set_edid(intel_dp);

status = connector_status_connected;

intel_dp_check_device_service_irq(intel_dp);

intel_dp_unset_edid(intel_dp);

if (!intel_dp_is_edp(intel_dp))

status,

intel_dp->dpcd,

intel_dp->downstream_ports);

static void

intel_dp_force(struct drm_connector *connector)

{

struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));

connector->base.id, connector->name);

return;

intel_dp_unset_edid(intel_dp);

intel_dp_set_edid(intel_dp);

}

{

int num_modes;

/* drm_edid_connector_update() done in ->detect() or ->force() */

/* Also add fixed mode, which may or may not be present in EDID */

if (num_modes)

return num_modes;

struct drm_display_mode *mode;

intel_dp->dpcd,

intel_dp->downstream_ports);

if (mode) {

num_modes++;

}

}

static int

intel_dp_connector_register(struct drm_connector *connector)

{

struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));

struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);

int ret;

ret = intel_connector_register(connector);

if (ret)

return ret;

intel_dp->aux.name, connector->kdev->kobj.name);

intel_dp->aux.dev = connector->kdev;

* ToDo: Clean this up to handle lspcon init and resume more

* efficiently and streamlined.

*/

drm_connector_attach_hdr_output_metadata_property(connector);

}

void intel_dp_connector_sync_state(struct intel_connector *connector,

const struct intel_crtc_state *crtc_state)

{

if (crtc_state && crtc_state->dsc.compression_enable) {

connector->dp.dsc_decompression_enabled = true;

} else {

connector->dp.dsc_decompression_enabled = false;

intel_dp_aux_fini(intel_dp);

}

{

intel_pps_vdd_off_sync(intel_dp);

intel_dp_tunnel_suspend(intel_dp);

}

{

intel_pps_wait_power_cycle(intel_dp);

}

static int intel_modeset_tile_group(struct intel_atomic_state *state,

int tile_group_id)

{

struct drm_connector_list_iter conn_iter;

struct drm_connector *connector;

int ret = 0;

drm_for_each_connector_iter(connector, &conn_iter) {

struct drm_connector_state *conn_state;

struct intel_crtc_state *crtc_state;

static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders)

{

struct intel_crtc *crtc;

if (transcoders == 0)

return 0;

struct intel_crtc_state *crtc_state;

int ret;

transcoders &= ~BIT(crtc_state->cpu_transcoder);

}

return 0;

}

static int intel_dp_connector_atomic_check(struct drm_connector *conn,

struct drm_atomic_state *_state)

{

struct intel_atomic_state *state = to_intel_atomic_state(_state);

struct drm_connector_state *conn_state = drm_atomic_get_new_connector_state(_state, conn);

struct intel_connector *intel_conn = to_intel_connector(conn);

return ret;

if (intel_dp_mst_source_support(intel_dp)) {

if (ret)

return ret;

}

* We don't enable port sync on BDW due to missing w/as and

* due to not having adjusted the modeset sequence appropriately.

*/

return 0;

if (conn->has_tile) {

static void intel_dp_oob_hotplug_event(struct drm_connector *connector,

enum drm_connector_status hpd_state)

{

struct intel_encoder *encoder = intel_attached_encoder(to_intel_connector(connector));

struct drm_i915_private *i915 = to_i915(connector->dev);

bool hpd_high = hpd_state == connector_status_connected;

bool need_work = false;

spin_lock_irq(&i915->irq_lock);

need_work = true;

}

spin_unlock_irq(&i915->irq_lock);

enum irqreturn

intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd)

{

struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);

struct intel_dp *intel_dp = &dig_port->dp;

u8 dpcd[DP_RECEIVER_CAP_SIZE];

* would end up in an endless cycle of

* "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..."

*/

"ignoring %s hpd on eDP [ENCODER:%d:%s]\n",

long_hpd ? "long" : "short",

dig_port->base.base.base.id,

return IRQ_HANDLED;

}

dig_port->base.base.base.id,

dig_port->base.base.name,

long_hpd ? "long" : "short");

return IRQ_HANDLED;

}

const struct intel_bios_encoder_data *devdata,

enum port port)

{

* eDP not supported on g4x. so bail out early just

* for a bit extra safety in case the VBT is bonkers.

*/

return false;

return true;

return devdata && intel_bios_encoder_supports_edp(devdata);

}

{

const struct intel_bios_encoder_data *devdata =

intel_bios_encoder_data_lookup(display, port);

}

bool

intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder)

{

enum port port = encoder->port;

if (intel_bios_encoder_is_lspcon(encoder->devdata))

return false;

return true;

if (port == PORT_A)

return false;

return true;

return false;

static void

intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)

{

enum port port = dp_to_dig_port(intel_dp)->base.port;

if (!intel_dp_is_edp(intel_dp))

drm_connector_attach_dp_subconnector_property(connector);

intel_attach_force_audio_property(connector);

intel_attach_broadcast_rgb_property(connector);

drm_connector_attach_max_bpc_property(connector, 6, 10);

drm_connector_attach_max_bpc_property(connector, 6, 12);

/* Register HDMI colorspace for case of lspcon */

if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))

drm_connector_attach_hdr_output_metadata_property(connector);

drm_connector_attach_vrr_capable_property(connector);

}

static void

intel_edp_add_properties(struct intel_dp *intel_dp)

{

struct intel_connector *connector = intel_dp->attached_connector;

const struct drm_display_mode *fixed_mode =

intel_panel_preferred_fixed_mode(connector);

intel_attach_scaling_mode_property(&connector->base);

drm_connector_set_panel_orientation_with_quirk(&connector->base,

fixed_mode->hdisplay,

fixed_mode->vdisplay);

}

static void intel_edp_backlight_setup(struct intel_dp *intel_dp,

struct intel_connector *connector)

{

enum pipe pipe = INVALID_PIPE;

pipe = vlv_pps_backlight_initial_pipe(intel_dp);

intel_backlight_setup(connector, pipe);

}

static bool intel_edp_init_connector(struct intel_dp *intel_dp,

{

struct intel_display *display = to_intel_display(intel_dp);

struct drm_display_mode *fixed_mode;

struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;

bool has_dpcd;

* with an already powered-on LVDS power sequencer.

*/

if (intel_get_lvds_encoder(dev_priv)) {

!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));

"LVDS was detected, not registering eDP\n");

return false;

}

encoder->devdata);

if (!intel_pps_init(intel_dp)) {

"[ENCODER:%d:%s] unusable PPS, disabling eDP\n",

encoder->base.base.id, encoder->base.name);

/*

intel_alpm_init_dpcd(intel_dp);

/* Cache DPCD and EDID for edp. */

if (!has_dpcd) {

/* if this fails, presume the device is a ghost */

"[ENCODER:%d:%s] failed to retrieve link info, disabling eDP\n",

encoder->base.base.id, encoder->base.name);

goto out_vdd_off;

* DPCD read? Would need sort out the VDD handling...

*/

if (!intel_digital_port_connected(encoder)) {

"[ENCODER:%d:%s] HPD is down, disabling eDP\n",

encoder->base.base.id, encoder->base.name);

goto out_vdd_off;

* back to checking for a VGA branch device. Only do this

* on known affected platforms to minimize false positives.

*/

(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) ==

DP_DWN_STRM_PORT_TYPE_ANALOG) {

"[ENCODER:%d:%s] VGA converter detected, disabling eDP\n",

encoder->base.base.id, encoder->base.name);

goto out_vdd_off;

}

}

if (!drm_edid) {

/* Fallback to EDID from ACPI OpRegion, if any */

if (drm_edid)

"[CONNECTOR:%d:%s] Using OpRegion EDID\n",

}

if (drm_edid) {

drm_edid_free(drm_edid);

drm_edid = ERR_PTR(-EINVAL);

}

drm_edid = ERR_PTR(-ENOENT);

}

IS_ERR(drm_edid) ? NULL : drm_edid);

/* MSO requires information from the EDID */

intel_edp_mso_init(intel_dp);

/* multiply the mode clock and horizontal timings for MSO */

/* fallback to VBT if available for eDP */

"[ENCODER:%d:%s] failed to find fixed mode for the panel, disabling eDP\n",

encoder->base.base.id, encoder->base.name);

goto out_vdd_off;

}

intel_edp_add_properties(intel_dp);

out_vdd_off:

intel_pps_vdd_off_sync(intel_dp);

return false;

}

bool

intel_dp_init_connector(struct intel_digital_port *dig_port,

{

struct intel_display *display = to_intel_display(dig_port);

struct intel_dp *intel_dp = &dig_port->dp;

int type;

if (drm_WARN(dev, dig_port->max_lanes < 1,

"Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n",

return false;

intel_dp->reset_link_params = true;

/* Preserve the current hw state. */

/*

* Currently we don't support eDP on TypeC ports for DISPLAY_VER < 30,

* although in theory it could work on TypeC legacy ports.

*/

type = DRM_MODE_CONNECTOR_eDP;

/* eDP only on port B and/or C on vlv/chv */

port != PORT_B && port != PORT_C))

return false;

} else {

intel_dp_set_default_sink_rates(intel_dp);

intel_dp_set_default_max_sink_lane_count(intel_dp);

vlv_pps_pipe_init(intel_dp);

intel_dp_aux_init(intel_dp);

"Adding %s connector on [ENCODER:%d:%s]\n",

type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",

type, &intel_dp->aux.ddc);

if (type != DRM_MODE_CONNECTOR_eDP)

else

intel_dp_aux_fini(intel_dp);

goto fail;

}

intel_dp_reset_link_params(intel_dp);

/* init MST on ports that can support it */

if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {

if (ret)

"HDCP init failed, skipping.\n");

}

return true;

fail:

return false;

}

{

struct intel_encoder *encoder;

return;

struct intel_dp *intel_dp;

if (encoder->type != INTEL_OUTPUT_DDI)

continue;

if (intel_dp->is_mst)

}

}

{

struct intel_encoder *encoder;

return;

struct intel_dp *intel_dp;

int ret;

if (!intel_dp_mst_source_support(intel_dp))

continue;

if (ret) {

intel_dp->is_mst = false;

}

}

}