int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);

/* command emit functions */

void (*emit_ib)(struct amdgpu_ring *ring,

void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,

uint64_t seq, unsigned flags);

void (*emit_pipeline_sync)(struct amdgpu_ring *ring);

#define AMDGPU_FENCE_FLAG_64BIT (1 << 0)

#define AMDGPU_FENCE_FLAG_INT (1 << 1)

int amdgpu_fence_driver_init(struct amdgpu_device *adev);

void amdgpu_fence_driver_fini(struct amdgpu_device *adev);

void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev);

struct drm_file *file_priv);

unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);

struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);

struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,

struct drm_gem_object *gobj,

int flags);

unsigned shared_count;

struct fence **shared;

struct fence_cb cb;

};

uint32_t length_dw;

uint64_t gpu_addr;

uint32_t *ptr;

uint32_t flags;

};

enum amdgpu_ring_type {

extern const struct amd_sched_backend_ops amdgpu_sched_ops;

int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,

int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,

struct amdgpu_job **job);

struct amdgpu_device *adev;

const struct amdgpu_ring_funcs *funcs;

struct amdgpu_fence_driver fence_drv;

spinlock_t fence_lock;

struct amdgpu_bo *ring_obj;

unsigned wptr_offs;

unsigned next_rptr_offs;

unsigned fence_offs;

enum amdgpu_ring_type type;

char name[16];

unsigned cond_exe_offs;

/* Scheduler entity for page table updates */

struct amd_sched_entity entity;

};

struct amdgpu_vm_id {

struct amdgpu_sync active;

struct fence *last_flush;

struct amdgpu_ring *last_user;

uint64_t pd_gpu_addr;

/* last flushed PD/PT update */

struct amdgpu_ring *vm_pte_rings[AMDGPU_MAX_RINGS];

unsigned vm_pte_num_rings;

atomic_t vm_pte_next_ring;

};

void amdgpu_vm_manager_init(struct amdgpu_device *adev);

uint32_t macrotile_mode_array[16];

};

struct amdgpu_gfx {

struct mutex gpu_clock_mutex;

struct amdgpu_gca_config config;

struct amdgpu_irq_src priv_reg_irq;

struct amdgpu_irq_src priv_inst_irq;

/* gfx status */

/* ce ram size*/

};

int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,

unsigned size, struct amdgpu_ib *ib);

int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,

struct amdgpu_ib *ib, struct fence *last_vm_update,

int amdgpu_ib_pool_init(struct amdgpu_device *adev);

void amdgpu_ib_pool_fini(struct amdgpu_device *adev);

int amdgpu_ib_ring_tests(struct amdgpu_device *adev);

struct amdgpu_cs_chunk {

uint32_t chunk_id;

uint32_t length_dw;

};

struct amdgpu_cs_parser {

struct amdgpu_job {

struct amd_sched_job base;

struct amdgpu_device *adev;

struct amdgpu_ring *ring;

struct amdgpu_sync sync;

struct amdgpu_ib *ibs;

struct fence *fence; /* the hw fence */

uint32_t num_ibs;

void *owner;

};

#define to_amdgpu_job(sched_job) \

container_of((sched_job), struct amdgpu_job, base)

struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];

struct amdgpu_irq_src trap_irq;

struct amdgpu_irq_src illegal_inst_irq;

};

/*

bool grbm_indexed;

};

/*

* ASIC specific functions.

*/

u32 (*get_xclk)(struct amdgpu_device *adev);

/* get the gpu clock counter */

uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);

/* MM block clocks */

int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);

int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);

bool shutdown;

bool need_dma32;

bool accel_working;

struct notifier_block acpi_nb;

struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];

struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];

#if defined(CONFIG_DEBUG_FS)

struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];

#endif

#define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))

#define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))

#define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))

#define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))

#define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))

#define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))

#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))

#define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))

#define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))

#define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))

#define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))

#define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))

#define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))

#define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))

#define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))

#define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))

#define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))

#define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))