diff options
Diffstat (limited to 'arch/arm64/boot/dts/sprd/sc9860.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/sprd/sc9860.dtsi | 69 |
1 files changed, 4 insertions, 65 deletions
diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi index d2456d633c39..765acde4867c 100644 --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi @@ -115,7 +115,7 @@ idle-states { entry-method = "psci"; - CORE_PD: core_pd { + CORE_PD: cpu-pd { compatible = "arm,idle-state"; entry-latency-us = <1000>; exit-latency-us = <700>; @@ -124,7 +124,7 @@ arm,psci-suspend-param = <0x00010002>; }; - CLUSTER_PD: cluster_pd { + CLUSTER_PD: cluster-pd { compatible = "arm,idle-state"; entry-latency-us = <1000>; exit-latency-us = <1000>; @@ -184,20 +184,6 @@ | IRQ_TYPE_LEVEL_HIGH)>; }; - pmu_gate: pmu-gate { - compatible = "sprd,sc9860-pmu-gate"; - sprd,syscon = <&pmu_regs>; /* 0x402b0000 */ - clocks = <&ext_26m>; - #clock-cells = <1>; - }; - - pll: pll { - compatible = "sprd,sc9860-pll"; - sprd,syscon = <&ana_regs>; /* 0x40400000 */ - clocks = <&pmu_gate 0>; - #clock-cells = <1>; - }; - ap_clk: clock-controller@20000000 { compatible = "sprd,sc9860-ap-clk"; reg = <0 0x20000000 0 0x400>; @@ -214,19 +200,6 @@ #clock-cells = <1>; }; - apahb_gate: apahb-gate { - compatible = "sprd,sc9860-apahb-gate"; - sprd,syscon = <&ap_ahb_regs>; /* 0x20210000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; - - aon_gate: aon-gate { - compatible = "sprd,sc9860-aon-gate"; - sprd,syscon = <&aon_regs>; /* 0x402e0000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; aonsecure_clk: clock-controller@40880000 { compatible = "sprd,sc9860-aonsecure-clk"; @@ -235,13 +208,6 @@ #clock-cells = <1>; }; - agcp_gate: agcp-gate { - compatible = "sprd,sc9860-agcp-gate"; - sprd,syscon = <&agcp_regs>; /* 0x415e0000 */ - clocks = <&aon_prediv 0>; - #clock-cells = <1>; - }; - gpu_clk: clock-controller@60200000 { compatible = "sprd,sc9860-gpu-clk"; reg = <0 0x60200000 0 0x400>; @@ -256,13 +222,6 @@ #clock-cells = <1>; }; - vsp_gate: vsp-gate { - compatible = "sprd,sc9860-vsp-gate"; - sprd,syscon = <&vsp_regs>; /* 0x61100000 */ - clocks = <&vsp_clk 0>; - #clock-cells = <1>; - }; - cam_clk: clock-controller@62000000 { compatible = "sprd,sc9860-cam-clk"; reg = <0 0x62000000 0 0x4000>; @@ -270,13 +229,6 @@ #clock-cells = <1>; }; - cam_gate: cam-gate { - compatible = "sprd,sc9860-cam-gate"; - sprd,syscon = <&cam_regs>; /* 0x62100000 */ - clocks = <&cam_clk 0>; - #clock-cells = <1>; - }; - disp_clk: clock-controller@63000000 { compatible = "sprd,sc9860-disp-clk"; reg = <0 0x63000000 0 0x400>; @@ -284,20 +236,6 @@ #clock-cells = <1>; }; - disp_gate: disp-gate { - compatible = "sprd,sc9860-disp-gate"; - sprd,syscon = <&disp_regs>; /* 0x63100000 */ - clocks = <&disp_clk 0>; - #clock-cells = <1>; - }; - - apapb_gate: apapb-gate { - compatible = "sprd,sc9860-apapb-gate"; - sprd,syscon = <&ap_apb_regs>; /* 0x70b00000 */ - clocks = <&ap_clk 0>; - #clock-cells = <1>; - }; - funnel@10001000 { /* SoC Funnel */ compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0 0x10001000 0 0x1000>; @@ -338,7 +276,8 @@ reg = <0 0x10003000 0 0x1000>; clocks = <&ext_26m>; clock-names = "apb_pclk"; - out-ports { + + in-ports { port { etb_in: endpoint { remote-endpoint = |