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-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dma.h12
-rw-r--r--drivers/gpu/drm/nouveau/nv17_fence.c38
-rw-r--r--drivers/gpu/drm/nouveau/nv84_fence.c19
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_fence.c18
4 files changed, 39 insertions, 48 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h
index 3e6c39d7ea01..3f86cdff927f 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.h
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.h
@@ -74,18 +74,6 @@ OUT_RING(struct nouveau_channel *chan, int data)
nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
}
-static inline void
-BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size)
-{
- OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
-}
-
-static inline void
-BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size)
-{
- OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
-}
-
#define WRITE_PUT(val) do { \
mb(); \
nouveau_bo_rd32(chan->push.buffer, 0); \
diff --git a/drivers/gpu/drm/nouveau/nv17_fence.c b/drivers/gpu/drm/nouveau/nv17_fence.c
index c27d225699a5..8d7b4f2479cc 100644
--- a/drivers/gpu/drm/nouveau/nv17_fence.c
+++ b/drivers/gpu/drm/nouveau/nv17_fence.c
@@ -21,15 +21,15 @@
*
* Authors: Ben Skeggs <bskeggs@redhat.com>
*/
-
-#include <nvif/os.h>
-#include <nvif/class.h>
-#include <nvif/cl0002.h>
-
#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nv10_fence.h"
+#include <nvif/push006c.h>
+
+#include <nvif/class.h>
+#include <nvif/cl0002.h>
+
int
nv17_fence_sync(struct nouveau_fence *fence,
struct nouveau_channel *prev, struct nouveau_channel *chan)
@@ -37,6 +37,8 @@ nv17_fence_sync(struct nouveau_fence *fence,
struct nouveau_cli *cli = (void *)prev->user.client;
struct nv10_fence_priv *priv = chan->drm->fence;
struct nv10_fence_chan *fctx = chan->fence;
+ struct nvif_push *ppush = prev->chan.push;
+ struct nvif_push *npush = chan->chan.push;
u32 value;
int ret;
@@ -48,23 +50,21 @@ nv17_fence_sync(struct nouveau_fence *fence,
priv->sequence += 2;
spin_unlock(&priv->lock);
- ret = RING_SPACE(prev, 5);
+ ret = PUSH_WAIT(ppush, 5);
if (!ret) {
- BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
- OUT_RING (prev, fctx->sema.handle);
- OUT_RING (prev, 0);
- OUT_RING (prev, value + 0);
- OUT_RING (prev, value + 1);
- FIRE_RING (prev);
+ PUSH_NVSQ(ppush, NV176E, NV11_SUBCHAN_DMA_SEMAPHORE, fctx->sema.handle,
+ NV11_SUBCHAN_SEMAPHORE_OFFSET, 0,
+ NV11_SUBCHAN_SEMAPHORE_ACQUIRE, value + 0,
+ NV11_SUBCHAN_SEMAPHORE_RELEASE, value + 1);
+ PUSH_KICK(ppush);
}
- if (!ret && !(ret = RING_SPACE(chan, 5))) {
- BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
- OUT_RING (chan, fctx->sema.handle);
- OUT_RING (chan, 0);
- OUT_RING (chan, value + 1);
- OUT_RING (chan, value + 2);
- FIRE_RING (chan);
+ if (!ret && !(ret = PUSH_WAIT(npush, 5))) {
+ PUSH_NVSQ(npush, NV176E, NV11_SUBCHAN_DMA_SEMAPHORE, fctx->sema.handle,
+ NV11_SUBCHAN_SEMAPHORE_OFFSET, 0,
+ NV11_SUBCHAN_SEMAPHORE_ACQUIRE, value + 1,
+ NV11_SUBCHAN_SEMAPHORE_RELEASE, value + 2);
+ PUSH_KICK(npush);
}
mutex_unlock(&cli->mutex);
diff --git a/drivers/gpu/drm/nouveau/nv84_fence.c b/drivers/gpu/drm/nouveau/nv84_fence.c
index 0c4b740abea8..bc09e64fe6b8 100644
--- a/drivers/gpu/drm/nouveau/nv84_fence.c
+++ b/drivers/gpu/drm/nouveau/nv84_fence.c
@@ -52,16 +52,17 @@ nv84_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
static int
nv84_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
- int ret = RING_SPACE(chan, 7);
+ struct nvif_push *push = chan->chan.push;
+ int ret = PUSH_WAIT(push, 7);
if (ret == 0) {
- BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
- OUT_RING (chan, chan->vram.handle);
- BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
- OUT_RING (chan, upper_32_bits(virtual));
- OUT_RING (chan, lower_32_bits(virtual));
- OUT_RING (chan, sequence);
- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
- FIRE_RING (chan);
+ PUSH_NVSQ(push, NV826F, NV11_SUBCHAN_DMA_SEMAPHORE, chan->vram.handle);
+ PUSH_NVSQ(push, NV826F,
+ NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
+ NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
+ NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
+ NV84_SUBCHAN_SEMAPHORE_TRIGGER,
+ NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
+ PUSH_KICK(push);
}
return ret;
}
diff --git a/drivers/gpu/drm/nouveau/nvc0_fence.c b/drivers/gpu/drm/nouveau/nvc0_fence.c
index e4b2efaee254..13b1345081d9 100644
--- a/drivers/gpu/drm/nouveau/nvc0_fence.c
+++ b/drivers/gpu/drm/nouveau/nvc0_fence.c
@@ -50,15 +50,17 @@ nvc0_fence_emit32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
static int
nvc0_fence_sync32(struct nouveau_channel *chan, u64 virtual, u32 sequence)
{
- int ret = RING_SPACE(chan, 5);
+ struct nvif_push *push = chan->chan.push;
+ int ret = PUSH_WAIT(push, 5);
if (ret == 0) {
- BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
- OUT_RING (chan, upper_32_bits(virtual));
- OUT_RING (chan, lower_32_bits(virtual));
- OUT_RING (chan, sequence);
- OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
- NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
- FIRE_RING (chan);
+ PUSH_NVSQ(push, NV906F,
+ NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, upper_32_bits(virtual),
+ NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW, lower_32_bits(virtual),
+ NV84_SUBCHAN_SEMAPHORE_SEQUENCE, sequence,
+ NV84_SUBCHAN_SEMAPHORE_TRIGGER,
+ NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL |
+ NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
+ PUSH_KICK(push);
}
return ret;
}